DCT
1:25-cv-00510
Valtrus Innovations Ltd v. Advanced Micro Devices Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Valtrus Innovations Ltd. (Republic of Ireland), Key Patent Innovations Limited (Republic of Ireland)
- Defendant: Advanced Micro Devices, Inc. (Delaware)
- Plaintiff’s Counsel: Ciccarelli Law Firm LLC
- Case Identification: 1:25-cv-00510, W.D. Tex., Filed 04/04/2025
- Venue Allegations: Venue is based on allegations that Defendant AMD maintains its principal place of business, has multiple regular and established places of business, and commits acts of infringement in the Western District of Texas.
- Core Dispute: Plaintiffs allege that Defendant’s multicore processors, including the EPYC, Ryzen, and Athlon series, infringe a patent related to methods for controlling access to protected computer system resources.
- Technical Context: The technology concerns processor architecture for secure computing, specifically a hardware-level mechanism to create a protected mode that can block even the most privileged software from accessing certain designated resources, forming a foundation for a hardware root of trust.
- Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of the patent-in-suit because Plaintiffs had previously asserted it against third parties, including customers of AMD, in litigation that implicated the accused products.
Case Timeline
| Date | Event |
|---|---|
| 2004-08-03 | '539 Patent Priority Date |
| 2011-04-19 | '539 Patent Issue Date |
| 2016-06-19 | Date of technical presentation on AMD Memory Encryption referenced in complaint |
| 2025-04-04 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 7,930,539, "Computer system resource access control," issued April 19, 2011.
The Invention Explained
- Problem Addressed: The patent describes a problem in computer architecture where conventional privilege levels (e.g., kernel vs. user mode) may be insufficient to protect certain critical system resources from being accessed or modified, even by the most-privileged software like the operating system. This could compromise system stability and security, particularly in complex, evolving architectures. ('539 Patent, col. 1:21-46).
- The Patented Solution: The invention discloses a method and device that implement a "protected mode of operation." When a computer system operates in this mode, requests to access pre-defined "protected resources" are denied outright, regardless of the privilege level of the software making the request. If the system is not in this protected mode, access requests are then processed according to conventional privilege-based rules. This creates a hardware-enforced barrier that can be activated to shield core resources from all software. ('539 Patent, Abstract; col. 8:38-50).
- Technical Importance: This approach provides a robust method for creating secure, isolated partitions within a computer system, a foundational concept for hardware-based security and virtualization technologies that rely on a root of trust independent of the main OS. ('539 Patent, col. 7:11-29).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 1. (Compl. ¶14).
- The essential elements of independent claim 1 are:
- Receiving a request from a software program to access a specified resource.
- Determining if the specified resource is a protected resource.
- If it is a protected resource, then performing one of two actions:
- If the system is in a "protected mode of operation," denying the request regardless of the software's privilege level (even a most-privileged level).
- If the system is not in a "protected mode of operation," processing the request based on the software program's associated access rights.
III. The Accused Instrumentality
Product Identification
The complaint names "AMD multicore processors, AMD EPYC processors, AMD Ryzen processors, and AMD Athlon processors," with a specific focus on the AMD EPYC 7003 Series processors as an exemplary product. (Compl. ¶¶15, 17).
Functionality and Market Context
The accused products are alleged to incorporate an "AMD Secure Processor," which is an integrated, ARM-based co-processor also known as the Platform Security coProcessor (PSP). (Compl. ¶17). This hardware creates a partitioned security environment with a "Normal world" and a "Secure world," analogous to ARM's TrustZone architecture. (Compl. ¶19). The complaint alleges that software in the "Normal world" can request access to resources in the "Secure world" via a "Secure Monitor Call" (SMC) instruction, which is arbitrated by a "Secure Monitor." (Compl. ¶¶21, 23). The complaint uses a diagram of the AMD Secure Processor to illustrate it as a dedicated security subsystem integrated within the main SoC. (Compl. p. 5).
IV. Analysis of Infringement Allegations
'539 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| receiving a request from a software program to access a specified one of the plurality of resources | A software program in the "Normal world," such as a TrustZone API driver, requests access to a resource on behalf of an application. This request is passed to the Secure Monitor. The complaint provides a diagram illustrating the flow from a user application to the Secure Monitor. (Compl. p. 7). | ¶¶18-19 | col. 9:20-24 |
| determining whether the specified one of the plurality of resources is a protected resource | The AMD Secure Processor determines whether a requested resource, such as secure application code, is located in the "Secure world," which the complaint equates to a "protected resource." | ¶¶20-21 | col. 9:35-39 |
| if the computer system is operating in a protected mode of operation, then denying the request regardless of access rights associated with the software program including software programs having a most-privileged level | The system operates in a "protected mode" when the Secure Monitor Call disable (SCD) bit in the Secure Configuration Register (SCR) is set to 1. This disables the SMC instruction, preventing entry to the Secure state and thereby denying the request to access the secure resource, regardless of the privilege level of the requesting software. A diagram from ARM documentation shows the function of the SCR.SCD bit. (Compl. p. 10). | ¶¶24-25 | col. 10:57-65 |
| processing the request based on the access rights associated with the software program if the computer system is not operating in the protected mode of operation | If the system is not in a "protected mode" (i.e., the SCR.SCD bit is 0), the SMC instruction is enabled, and the request to enter the Secure state is processed based on access rights, such as whether the software is executing at a sufficient privilege level (e.g., PL1 or higher) to use the SMC instruction. | ¶¶26-27 | col. 11:5-10 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the functionality of AMD's Secure Processor, which is based on ARM's TrustZone architecture, falls within the scope of the patent's claims. The complaint uses ARM technical documentation to describe the accused functionality. The court may need to determine if terms like "protected mode of operation," filed in 2004, can be properly construed to read on the specific implementation of an "SCR.SCD" bit disabling an "SMC" instruction in a modern processor.
- Technical Questions: The complaint alleges that making the "SMC" instruction "UNDEFINED" or "UNPREDICTABLE" by setting the "SCD" bit constitutes "denying the request" as claimed. A potential point of dispute is whether disabling the mechanism for making a request is technically the same as receiving a request and then actively denying it, as depicted in the patent's flowcharts (e.g., '539 Patent, Fig. 5, step 510).
V. Key Claim Terms for Construction
The Term: "protected mode of operation"
- Context and Importance: This term is the lynchpin of the asserted claim. The infringement case depends on whether the accused processors' state—when the "SCR.SCD" bit is set to 1—constitutes this claimed "mode."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim itself defines the mode functionally as one in which requests to protected resources are denied "regardless of access rights... including a most-privileged level." ('539 Patent, col. 17:25-29). Plaintiffs may argue that any mechanism achieving this functional outcome meets the claim.
- Evidence for a Narrower Interpretation: The specification describes specific embodiments, such as a "protected mode indicator" bit ("PM") in a register, that explicitly signals the mode. ('539 Patent, col. 8:38-50). A defendant could argue the term should be limited to systems with such an explicit indicator, rather than inferring the mode from the state of a different functional bit ("SCD").
The Term: "denying the request"
- Context and Importance: Practitioners may focus on this term because the accused functionality involves making an instruction ("SMC") non-functional, which may differ from an active denial of a successfully transmitted request.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain and ordinary meaning could encompass any action that prevents the requested access from occurring. The patent's summary describes the outcome as "denying the request if the computer system is operating in a protected mode." ('539 Patent, col. 2:54-56).
- Evidence for a Narrower Interpretation: The patent's flowchart in Figure 5 depicts a distinct "DENY REQUEST" step (510) that occurs after checks for a protected resource and the protected mode have been made. ('539 Patent, Fig. 5). This could support an interpretation that "denying" requires an affirmative rejection of a cognizable request, rather than causing the instruction that forms the request to fail or become undefined.
VI. Other Allegations
- Indirect Infringement: The complaint alleges that AMD induces infringement by selling the accused processors "with the intent to encourage and facilitate infringing uses." (Compl. ¶29). The complaint does not, however, plead specific facts detailing how AMD provides instructions or encouragement for customers to operate the products in the specific manner that allegedly satisfies all steps of the claimed method.
- Willful Infringement: The willfulness allegation is based on alleged pre-suit knowledge. The complaint asserts this knowledge arises from Plaintiffs' prior infringement litigation against AMD's customers, which allegedly involved the same patent and implicated the accused AMD products. (Compl. ¶¶28, 32).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "protected mode of operation," as defined in a 2004-filed patent, be construed to read on the specific function of an "SCD" bit that disables "SMC" instructions within the ARM-based security architecture used in modern AMD processors?
- A key evidentiary question will be one of technical equivalence: does making an instruction non-functional or "undefined," as the accused products allegedly do, constitute "denying the request" as required by the claim, or is there a fundamental mismatch between this behavior and the active denial process illustrated in the patent's specification?
- Finally, a legal question regarding damages will be whether knowledge of infringement suits against one's customers is sufficient to establish the "wanton, malicious, and egregious" conduct required to support a claim for willful infringement against the component supplier.