DCT

1:25-cv-00552

Eireog Innovations Ltd v. Amazon Web Services Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00552, W.D. Tex., 07/07/2025
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is registered to do business in Texas, has transacted business in the Western District of Texas, and maintains a regular and established place of business within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s cloud computing services, which utilize specific Intel and AMD processor architectures, infringe four patents related to processor-level technologies for interrupt management, cache coherency, and decorated instruction processing.
  • Technical Context: The patents address low-level processor architecture optimizations designed to improve performance and efficiency in multi-core, virtualized computing environments, which are foundational to modern large-scale cloud infrastructure.
  • Key Procedural History: The current filing is an amended complaint. The complaint alleges that Defendant has been on notice of the asserted patents and its infringement since at least the filing of the original complaint on April 11, 2025, which may form the basis for allegations of post-suit willful infringement.

Case Timeline

Date Event
2009-05-07 U.S. Patent No. 8,117,399 Priority Date
2010-09-21 U.S. Patent No. 8,504,777 Priority Date
2012-02-14 U.S. Patent No. 8,117,399 Issues
2012-08-09 U.S. Patent Nos. 9,436,626 & 9,442,870 Priority Date
2013-08-06 U.S. Patent No. 8,504,777 Issues
2016-09-06 U.S. Patent No. 9,436,626 Issues
2016-09-13 U.S. Patent No. 9,442,870 Issues
2025-04-11 Original Complaint Filing Date
2025-07-07 Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,436,626 - “Processor interrupt interface with interrupt partitioning and virtualization enhancements”

  • Patent Identification: U.S. Patent No. 9,436,626, “Processor interrupt interface with interrupt partitioning and virtualization enhancements,” issued September 6, 2016 (Compl. ¶8).

The Invention Explained

  • Problem Addressed: In data processing systems with multiple processors or virtualized partitions, interrupt processing can be delayed when multiple processors compete for access to a central interrupt controller. This adds software complexity and degrades system performance, particularly in partitioned environments where interrupts must be managed for distinct entities like a hypervisor and multiple guest operating systems (’626 Patent, col. 1:11-44).
  • The Patented Solution: The invention moves interrupt management logic, such as priority blocking, from a centralized controller directly into the processor core itself. It achieves this using “special purpose registers” on the processor core that store partition-specific information like partition identifiers and priority levels. An interrupt request is delivered to the core over a shared interface along with its associated context (e.g., its target partition ID and priority), allowing the core to evaluate blocking conditions locally without hypervisor intervention or memory-mapped operations to an external controller (’626 Patent, col. 2:15-34; Abstract).
  • Technical Importance: This architecture simplifies interrupt controller design and reduces latency, which is critical for performance and security in virtualized cloud computing environments where efficient management of hardware resources across different tenants is paramount (’626 Patent, col. 2:5-14).

Key Claims at a Glance

  • The complaint indicates it will rely on exemplary independent claim 1 (Compl. ¶10).
  • Claim 1 of the ’626 Patent recites a method with the following essential elements:
    • Receiving, at a processor, an interrupt package containing a first interrupt request, an interrupt identifier, a partition identifier, a priority value, and a thread identifier.
    • Processing the interrupt package against one or more partitions running on the processor.
    • This processing involves comparing the received priority value and partition identifier against a stored priority level and stored partition identifier retrieved from special purpose registers at the processor.
    • The purpose of the comparison is to determine, on a partition basis, whether the interrupt request is blocked or forwarded to a targeted thread.

U.S. Patent No. 9,442,870 - “Interrupt priority management using partition-based priority blocking processor registers”

  • Patent Identification: U.S. Patent No. 9,442,870, “Interrupt priority management using partition-based priority blocking processor registers,” issued September 13, 2016 (Compl. ¶18).

The Invention Explained

  • Problem Addressed: The patent describes the need for a more efficient way to manage interrupt priority in systems with multiple partitions, noting that conventional mechanisms lack partition-based blocking and create performance issues due to controller access times (’870 Patent, col. 1:12-24).
  • The Patented Solution: The invention provides a processor core architecture that includes special purpose priority blocking registers (e.g., an "INTLEVEL" register for a hypervisor and a "GINTLEVEL" register for a guest OS). Software can use these registers to set distinct priority thresholds for different partitions. When an interrupt arrives, its associated partition identifier is used to select the appropriate register, and its priority level is compared against the value in that register to determine if the interrupt should be blocked or accepted by the targeted partition (’870 Patent, col. 2:2-24; Abstract).
  • Technical Importance: This method allows for independent, partition-aware interrupt management to be performed directly on the processor core, reducing software overhead and latency compared to systems that rely on a centralized controller or hypervisor for such decisions (’870 Patent, col. 2:8-15).

Key Claims at a Glance

  • The complaint indicates it will rely on exemplary independent claim 1 (Compl. ¶20).
  • Claim 1 of the ’870 Patent recites a method with the following essential elements:
    • Receiving, at a processor, an interrupt package for a physical interrupt request, which includes a priority value and a partition identifier.
    • Processing the package against one or more partitions on the processor.
    • The processing involves comparing the priority value and partition identifier against a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor.
    • This comparison determines on a partition basis whether the physical interrupt request is blocked or forwarded.

U.S. Patent No. 8,504,777 - “Data processor for processing decorated instructions with cache bypass”

  • Patent Identification: U.S. Patent No. 8,504,777, “Data processor for processing decorated instructions with cache bypass,” issued August 6, 2013 (Compl. ¶28).
  • Technology Synopsis: The patent addresses performance issues in multi-processor systems when performing atomic operations, such as incrementing a shared counter, which can cause system delays and resource contention (’777 Patent, col. 1:12-32). The described solution involves a “decorated instruction” that offloads the atomic read-modify-write operation to an intelligent memory device and explicitly bypasses the processor's cache, thereby avoiding cache coherency traffic and potential inaccuracies (’777 Patent, col. 2:8-24, 2:48-67).
  • Asserted Claims: The complaint identifies exemplary independent claim 16 (Compl. ¶30).
  • Accused Features: The complaint alleges that "accused cache processing features" within certain Intel (Skylake-based and newer) and AMD (EPYC series) CPUs used in AWS products infringe the ’777 Patent (Compl. ¶¶29, 33).

U.S. Patent No. 8,117,399 - “Processing of coherent and incoherent accesses at a uniform cache”

  • Patent Identification: U.S. Patent No. 8,117,399, “Processing of coherent and incoherent accesses at a uniform cache,” issued February 14, 2012 (Compl. ¶38).
  • Technology Synopsis: The patent addresses the problem of interconnect congestion in multi-core processors caused by cache coherency "snoop" operations that query other cores for updated data (’399 Patent, col. 1:12-25). The invention proposes marking individual cachelines as either "coherent" or "incoherent." A coherent read access (e.g., for data) that targets an incoherent cacheline is treated as a cache miss to ensure the latest data is fetched, while an incoherent read access (e.g., for an instruction) can result in a hit on either type of line, reducing unnecessary snoops and bus traffic (’399 Patent, col. 2:1-11; Abstract).
  • Asserted Claims: The complaint identifies exemplary independent claim 14 (Compl. ¶40).
  • Accused Features: The complaint alleges that "accused cache processing features" within certain Intel (Skylake-based and newer) and AMD (EPYC series) CPUs used in AWS products infringe the ’399 Patent (Compl. ¶¶39, 43).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies a broad range of Amazon Web Services products as the "Accused Products." This includes numerous Amazon EC2 instance types (e.g., Accelerated Computing, General Purpose, Compute Optimized), AWS Lambda, AWS Cloudfront, AWS S3, and Amazon Elastic Kubernetes Service, among others (Compl. ¶¶9, 19, 29, 39).

Functionality and Market Context

  • The common element among the accused services is their alleged use of underlying CPUs from Intel (Haswell, Skylake, and newer architectures) and AMD (Zen-based and EPYC series architectures) (Compl. ¶¶9, 29, 39). The complaint alleges that these processors incorporate the patented technologies for interrupt management and cache processing, which are fundamental to the operation of the virtualized computing environments that AWS offers to its customers. The complaint cites AWS's own documentation regarding its instance types and the processors they use (Compl. ¶12, Ex. 4-8).

IV. Analysis of Infringement Allegations

The complaint references claim-chart exhibits that are not provided; therefore, the narrative infringement theory is summarized below.

No probative visual evidence provided in complaint.

  • ’626 and ’870 Patent Infringement Allegations

    • The complaint alleges that the Accused Products directly infringe the ’626 and ’870 patents because the underlying Intel and AMD CPUs they utilize necessarily practice the claimed methods for managing interrupts (Compl. ¶¶10, 20). The narrative theory suggests that to function as modern virtualized processors, these CPUs must implement partition-aware, on-core interrupt blocking using specialized registers to handle requests for different logical partitions (such as a hypervisor or multiple guest operating systems), thereby meeting the limitations of the asserted claims.

  • Identified Points of Contention:

    • Scope Questions: A central question may be whether the term "partition", as used in the patents, can be construed to map directly onto the specific virtualization and security constructs (e.g., enclaves, virtual machines) implemented by the accused CPUs and offered in AWS services.
    • Technical Questions: The infringement analysis will raise the question of whether the interrupt handling mechanisms in modern Intel and AMD CPUs operate in the specific manner claimed—namely, by using a received partition ID to select a corresponding special purpose register that stores a priority threshold for comparison—or if they achieve partition-aware interrupt handling through a technically distinct process.

V. Key Claim Terms for Construction

  • The Term: "special purpose registers at the processor" (’626 Patent, Claim 1)
    • Context and Importance: This term is central because the invention's novelty lies in moving interrupt logic to these specific on-processor registers. The dispute will likely focus on whether the accused processors' registers, which may serve multiple functions, qualify as "special purpose" for partition-based interrupt blocking as described in the patent.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the function of these registers as being used "to evaluate partition ownership information, priority, and interrupt IDs" (’626 Patent, col. 2:21-23). This functional language could support a construction that covers any set of registers performing this role.
      • Evidence for a Narrower Interpretation: The detailed description identifies specific registers by name, such as "LPID registers 35", "INTLEVEL registers 36", and "EPR 37" (’626 Patent, col. 5:3-10). This may support an argument that the term is limited to registers with the specific structures and roles disclosed in the embodiments.
  • The Term: "partition-based priority blocking" (’870 Patent, Title)
    • Context and Importance: This phrase encapsulates the core inventive concept. The case may turn on whether the accused CPUs perform blocking that is truly "partition-based" as envisioned by the patent, or if they use a more general priority scheme that is not explicitly tied to partition identifiers in the claimed manner.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The abstract states the invention uses a "processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers" (’870 Patent, Abstract). Plaintiff may argue that any mechanism where interrupt priority is influenced by partition context falls within this description.
      • Evidence for a Narrower Interpretation: The specification describes a specific process where a partition identifier (LPID) is used to select a corresponding priority blocking register (e.g., "INTLEVEL" or "GINTLEVEL"), whose stored value is then compared to the interrupt's priority (’870 Patent, col. 2:13-24). This could support a narrower construction requiring this specific selection-and-comparison logic.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all four patents. It asserts that AWS provides customers with instructions, user guides, and marketing materials that "actively encourage and instruct" them to configure and use the Accused Products in a way that infringes (e.g., Compl. ¶¶12, 22, 32, 42). The cited materials include AWS web pages describing its EC2 instance types and the underlying processors (Compl. ¶12, Ex. 4-8).
  • Willful Infringement: The complaint does not contain the word "willful," but for each patent, it alleges that AWS has had knowledge of the patent and its infringing activities "At least as of the filing and service of the original complaint on April 11, 2025," and that AWS has continued to infringe despite this knowledge (e.g., Compl. ¶¶12, 22). These allegations establish a basis for a claim of post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technical operation: Does the microarchitecture of the accused Intel and AMD CPUs, as implemented in AWS services, actually perform interrupt and cache management as specifically claimed in the patents, or do they achieve similar high-level goals (e.g., efficient virtualization) through fundamentally different technical means?
  • A central question of claim construction will be whether terms rooted in the patents' specific disclosed embodiments, such as "special purpose registers" and "partition-based priority blocking," can be construed broadly enough to read on the complex and multi-functional hardware systems found in modern commercial processors.
  • A key question for indirect infringement will be one of intent: Does AWS's general documentation on configuring and using its cloud services constitute specific intent to encourage infringement of the underlying, low-level patented CPU features, or are such instructions too remote from the claimed invention to support a finding of inducement?