DCT

1:25-cv-00677

MOSAID Tech Inc v. Intel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00677, W.D. Tex., 05/06/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Intel operates a substantial research and development campus in Austin with over 1,400 employees and has committed the alleged acts of infringement within the District.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor devices manufactured using its advanced process nodes (including Intel 3, 4, 7, 10 nm, 16, and 22FFL) infringe eleven patents related to fundamental semiconductor design, layout, and fabrication technology.
  • Technical Context: The patents-in-suit cover a range of semiconductor technologies, including transistor layout rules to mitigate electrical interference, SRAM cell architecture to reduce manufacturing complexity, and FinFET transistor structures designed to enhance performance.
  • Key Procedural History: The complaint asserts a large, interrelated patent portfolio, with many of the patents-in-suit identified as divisionals or continuations of one another. No prior litigation or post-grant proceedings are mentioned in the complaint.

Case Timeline

Date Event
2006-08-31 ’757 Patent Priority Date
2006-12-18 ’957 Patent Priority Date
2007-05-29 ’577 Patent Family Priority Date
2007-07-09 ’433 Patent Priority Date
2008-08-29 ’655 Patent Priority Date
2009-01-13 ’957 Patent Issue Date
2009-04-07 ’757 Patent Issue Date
2010-10-13 ’517, ’940, ’300, ’215, ’091 Patent Family Priority Date
2010-11-30 ’577 Patent Issue Date
2012-12-25 ’909 Patent Issue Date
2013-05-14 ’517 Patent Issue Date
2014-08-19 ’940 Patent Issue Date
2015-12-08 ’300 Patent Issue Date
2016-05-24 ’655 Patent Issue Date
2016-06-28 ’215 Patent Issue Date
2017-02-07 ’433 Patent Issue Date
2017-07-25 ’091 Patent Issue Date
2025-05-06 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,476,957 - “Semiconductor Integrated Circuit”

  • Patent Identification: U.S. Patent No. 7,476,957, entitled “Semiconductor Integrated Circuit,” issued January 13, 2009. (Compl. ¶23).

The Invention Explained

  • Problem Addressed: The patent’s background section describes the "well proximity effect," a phenomenon in which the electrical characteristics of a transistor fluctuate depending on its closeness to the boundary of its semiconductor "well." (’957 Patent, col. 1:49-55). This effect complicates circuit design, as it makes transistor performance less predictable and circuit simulation less accurate. (’957 Patent, col. 2:48-55).
  • The Patented Solution: The invention proposes a specific circuit layout methodology to counteract this problem. It requires that different-sized transistors within the same well be arranged so that the center points of their active regions are equidistant from the well boundary. (’957 Patent, col. 3:11-20). By equalizing this distance, the layout ensures that each transistor experiences a consistent well proximity effect, which minimizes performance variations across the circuit. (’957 Patent, Fig. 1; Abstract).
  • Technical Importance: This design rule provides a method for creating more predictable and uniform transistor behavior, which is critical for enabling accurate simulation and reducing development time for complex integrated circuits. (’957 Patent, col. 4:38-44).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1. (Compl. ¶102).
  • The essential elements of claim 1 include:
    • A first well region and an adjacent second well region contacting at a well boundary.
    • A first active region of a certain size within the first well.
    • A second active region of a different size, also within the first well.
    • A specific geometric constraint: the distance from the well boundary to the halfway point of the first active region is “substantially the same” as the distance from the well boundary to the halfway point of the second active region. (Compl. ¶27).
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,514,757 - “Memory Formation with Reduced Metallization Layers”

  • Patent Identification: U.S. Patent No. 7,514,757, entitled “Memory Formation with Reduced Metallization Layers,” issued April 7, 2009. (Compl. ¶29).

The Invention Explained

  • Problem Addressed: The patent states that conventional Static Random-Access Memory (SRAM) cells typically require at least three metal layers for internal wiring, which increases manufacturing complexity. (’757 Patent, col. 1:26-31). Furthermore, the long vertical contacts required to connect these metal layers down to the transistors create high parasitic capacitance, which increases RC delay and slows memory performance. (’757 Patent, col. 1:31-38).
  • The Patented Solution: The invention describes a revised SRAM cell structure that utilizes a large, shared "first-layer contact" situated in the lower portion of the inter-layer dielectric (ILD). This contact provides the local interconnections between multiple transistors within the cell. (’757 Patent, Abstract). This approach frees up the first metallization layer for other routing, potentially reducing the total number of metal layers needed and allowing for shorter, lower-capacitance contacts. (’757 Patent, col. 2:1-12).
  • Technical Importance: This architecture aimed to reduce the manufacturing cost and improve the operational speed of SRAM cells, which are fundamental building blocks for on-chip cache memory in high-performance processors. (’757 Patent, col. 2:28-34).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1. (Compl. ¶117).
  • The essential elements of claim 1 include:
    • An SRAM cell with pull-up, pull-down, and pass-gate MOS devices.
    • A first metallization layer situated above an inter-layer dielectric (ILD) that has upper and lower portions.
    • A "first first-layer contact" located in the lower portion of the ILD, which connects at least two of the cell's devices and is physically isolated from other contacts in the upper portion.
    • A "second first-layer contact," also in the lower ILD portion.
    • A "second-layer contact" that sits on the second first-layer contact and electrically connects it to a bit-line or power line. (Compl. ¶32).
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,349,655 - “Method for Mechanical Stress Enhancement in Semiconductor Devices”

  • Patent Identification: U.S. Patent No. 9,349,655, “Method for Mechanical Stress Enhancement in Semiconductor Devices,” issued May 24, 2016. (Compl. ¶34).
  • Technology Synopsis: The patent relates to an integrated circuit structure designed to manage mechanical stress, a critical factor in transistor performance. The claimed invention involves placing a "first dummy gate" next to an operational device that has a strained channel, and a "second dummy gate" on an adjacent "dummy active region," with the two regions separated by shallow trench isolation (STI). (Compl. ¶38).
  • Asserted Claims: At least independent claim 1. (Compl. ¶132).
  • Accused Features: The complaint accuses instrumentalities made using an Intel 10 nm or Intel 7 fabrication process. (Compl. ¶131).

U.S. Patent No. 8,809,940 - “Fin Held Effect Transistor”

  • Patent Identification: U.S. Patent No. 8,809,940, “Fin Held Effect Transistor,” issued August 19, 2014. (Compl. ¶40).
  • Technology Synopsis: This patent relates to the structure of a fin field effect transistor (FinFET). The invention claims a fin that extends above adjacent insulation regions, where the fin itself comprises both a recessed portion (lower than the insulation regions) and a non-recessed portion (higher than the insulation regions), with a gate stack formed over the non-recessed portion. (Compl. ¶44).
  • Asserted Claims: At least independent claim 1. (Compl. ¶148).
  • Accused Features: The complaint accuses instrumentalities made using a 22FFL, Intel 16, Intel 3, or Intel 4 fabrication process. (Compl. ¶147).

U.S. Patent No. 8,440,517 - “FinFET and Method of Fabricating the Same”

  • Patent Identification: U.S. Patent No. 8,440,517, “FinFET and Method of Fabricating the Same,” issued May 14, 2013. (Compl. ¶46).
  • Technology Synopsis: The patent claims a method for fabricating a FinFET. The method involves forming a gate stack, recessing portions of the fin not covered by the gate, etching the corners of adjacent insulation regions to form tapered surfaces, and then selectively growing a strained material over the recessed fin portions and tapered surfaces. (Compl. ¶49).
  • Asserted Claims: At least independent claim 1. (Compl. ¶163).
  • Accused Features: The complaint accuses instrumentalities made using a 22FFL, Intel 16, Intel 3, or Intel 4 fabrication process. (Compl. ¶162).

U.S. Patent No. 9,209,300 - “Fin Field Effect Transistor”

  • Patent Identification: U.S. Patent No. 9,209,300, “Fin Field Effect Transistor,” issued December 8, 2015. (Compl. ¶51).
  • Technology Synopsis: This patent is directed to a FinFET structure. The claimed transistor includes first and second insulation regions with tapered top surfaces, and a fin extending between them that has a first portion with a top surface below the tapered surfaces and a second portion with a top surface above the tapered surfaces. (Compl. ¶55).
  • Asserted Claims: At least independent claim 1. (Compl. ¶175).
  • Accused Features: The complaint accuses instrumentalities made using a 22FFL, Intel 16, Intel 3, or Intel 4 fabrication process. (Compl. ¶174).

U.S. Patent No. 9,379,215 - “Fin Field Effect Transistor”

  • Patent Identification: U.S. Patent No. 9,379,215, “Fin Field Effect Transistor,” issued June 28, 2016. (Compl. ¶57).
  • Technology Synopsis: The patent claims a method for fabricating a FinFET. The key steps include forming a fin between two insulation regions, forming a gate stack over a portion of the fin, and then tapering the top surfaces of the insulation regions that are not covered by the gate stack. (Compl. ¶61).
  • Asserted Claims: At least independent claim 1. (Compl. ¶190).
  • Accused Features: The complaint accuses instrumentalities made using a 22FFL, Intel 16, Intel 3, or Intel 4 fabrication process. (Compl. ¶189).

U.S. Patent No. 9,716,091 - “Fin Field Effect Transistor”

  • Patent Identification: U.S. Patent No. 9,716,091, “Fin Field Effect Transistor,” issued July 25, 2017. (Compl. ¶63).
  • Technology Synopsis: This patent claims a FinFET structure comprising two fins separated by an insulation region with a tapered top surface. A portion of each fin extends above this tapered surface, a gate stack is formed over these portions, and a semiconductor material adjacent to the gate stack forms a source or drain. (Compl. ¶67).
  • Asserted Claims: At least independent claim 11. (Compl. ¶202).
  • Accused Features: The complaint accuses instrumentalities made using a 22FFL, Intel 16, Intel 3, or Intel 4 fabrication process. (Compl. ¶201).

U.S. Patent No. 7,842,577 - “Semiconductor Device and Method for Manufacturing the Same”

  • Patent Identification: U.S. Patent No. 7,842,577, “Semiconductor Device and Method for Manufacturing the Same,” issued November 30, 2010. (Compl. ¶69).
  • Technology Synopsis: The patent describes a manufacturing method involving a "two-step" isolation process. A first isolation region is formed, then a MOS device (including source/drain) is formed, and finally a second isolation region is formed by etching a portion of the source/drain region to create a trench and filling it with an inter-layer dielectric. (Compl. ¶¶72, 16).
  • Asserted Claims: At least independent claim 1. (Compl. ¶217).
  • Accused Features: The complaint accuses instrumentalities made using an Intel 10 nm, Intel 7, Intel 4, or Intel 3 fabrication process. (Compl. ¶216).

U.S. Patent No. 8,338,909 - “Two-Step STI Formation Process”

  • Patent Identification: U.S. Patent No. 8,338,909, “Two-Step STI Formation Process,” issued December 25, 2012. (Compl. ¶74).
  • Technology Synopsis: This patent claims an integrated circuit structure resulting from a two-step isolation process. The structure includes a first STI region, a gate electrode, and a second STI region formed from a trench filled with an inter-layer dielectric (ILD), where a contact etch stop layer (CESL) underlying the ILD does not extend into the trench. (Compl. ¶78).
  • Asserted Claims: At least independent claim 1. (Compl. ¶229).
  • Accused Features: The complaint accuses instrumentalities made using an Intel 10 nm, Intel 7, Intel 4, or Intel 3 fabrication process. (Compl. ¶228).

U.S. Patent No. 9,564,433 - “Semiconductor Device with Improved Contact Structure and Method of Forming the Same”

  • Patent Identification: U.S. Patent No. 9,564,433, “Semiconductor Device with Improved Contact Structure and Method of Forming the Same,” issued February 7, 2017. (Compl. ¶80).
  • Technology Synopsis: The patent claims a method for forming contacts in a MOS transistor. The method involves forming a first contact over a source/drain feature and then a second contact over the first contact and the gate stack, with the second contact continuously physically contacting both the first contact and a sidewall spacer on the gate stack. (Compl. ¶84).
  • Asserted Claims: At least independent claim 8. (Compl. ¶243).
  • Accused Features: The complaint accuses instrumentalities made using an Intel 10 nm and Intel 7 fabrication process. (Compl. ¶242).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are a wide range of Intel's semiconductor devices, including processors, graphics chips, FPGAs, and server products, manufactured using its 22FFL, Intel 16, Intel 10 nm, Intel 7, Intel 4, and Intel 3 process nodes. (Compl. ¶8). The complaint also extends allegations to devices Intel manufactures for third-party "Foundry Customers" such as Cisco and Amazon Web Services using these same processes. (Compl. ¶14).

Functionality and Market Context

  • The complaint alleges that the infringing features are not optional functionalities but are inherent to the physical structure and layout of the transistors and circuits as dictated by Intel's fundamental manufacturing processes. (Compl. ¶¶96-97). These rules are allegedly enforced through Intel’s Process Design Kits (PDKs) and Electronic Design Automation (EDA) tools, which customers must use to design chips for fabrication at Intel's foundries. (Compl. ¶¶16, 99). These semiconductor products are described as core components for a variety of electronic devices, including servers and computers sold by major customers like Dell Technologies. (Compl. ¶¶15, 94-95).
  • No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references claim chart exhibits that are not provided; therefore, the infringement allegations for the lead patents are summarized below in prose.

The complaint alleges that Intel’s semiconductor devices manufactured using its Intel 7 fabrication process, and other similar processes, directly infringe at least Claim 1 of the ’957 Patent. (Compl. ¶¶101-103). The infringement theory appears to be based on structural inherency. MOSAID alleges that Intel’s process-design rules, which are embedded in its PDKs and enforced through EDA verification tools, dictate the physical layout of transistors on the chip. (Compl. ¶¶96, 99). The complaint suggests that these mandatory design rules automatically cause the creation of the layout claimed in the ’957 Patent—specifically, the arrangement of different-sized active regions whose centers are equidistant from a well boundary—during the design and manufacturing flow. (Compl. ¶¶99, 107).

For the ’757 Patent, the complaint alleges that devices made using Intel's 22FFL or Intel 16 processes infringe at least Claim 1. (Compl. ¶¶116-118). The narrative theory is that the SRAM cells within these devices are built using the core structure claimed in the patent: a large, shared "first-layer contact" located in a lower portion of the inter-layer dielectric (ILD) that handles local connections between multiple transistors. (Compl. ¶32). This structure is the basis of the patent’s asserted improvement for reducing metallization layers and RC delay.

  • Identified Points of Contention:
    • Scope Questions: For the ’957 Patent, a central question may be the scope of the term “substantially the same” as it applies to the distance from the well boundary. The dispute could center on whether this term encompasses the inherent process variations present in high-volume semiconductor manufacturing. For the ’757 Patent, the definitions of the “lower portion” and “upper portion” of the ILD, and whether Intel's products have a corresponding physical demarcation, may be a key point of contention.
    • Technical Questions: A primary evidentiary question for the ’957 Patent will be what proof, beyond general allegations about design kits, demonstrates that the final manufactured active regions in Intel’s products are aligned as claimed. For the ’757 Patent, a technical question may be whether the alleged “first first-layer contact” in the accused devices is a single, physically isolated structure as described by the claim, or a different type of interconnect that achieves a similar electrical result.

V. Key Claim Terms for Construction

  • The Term: "substantially the same" (’957 Patent, Claim 1)

  • Context and Importance: This term is critical because it governs the degree of precision required for the alignment of the active regions. The viability of the infringement allegation depends on whether this term is construed narrowly to require near-perfect geometric alignment, or more broadly to accommodate typical manufacturing tolerances.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification's objective is to make the influence of the well proximity effect equal across transistors, which "can be prevented from varying among the transistors with different sizes." (’957 Patent, col. 5:49-53). This focus on functional effect rather than pure geometry may support a broader reading that allows for minor physical deviations so long as the electrical effect is equalized.
    • Evidence for a Narrower Interpretation: Figure 1 of the patent and its associated equations (e.g., "STIn1+0.5Wn1=STIn2+0.5Wn2") depict and describe a precise mathematical equality for the center-point distances. (’957 Patent, Fig. 1). This may support a narrower construction that requires strict adherence to the geometric principle shown.

  • The Term: "first first-layer contact" (’757 Patent, Claim 1)

  • Context and Importance: This term defines the core structural element of the invention. Practitioners may focus on this term because its construction will determine whether Intel's local interconnect structures meet this key limitation, particularly whether the term requires a single, continuous conductive body or can read on a set of electrically-coupled but distinct vias.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claim requires the contact to be in the "lower portion of the ILD" and to be "connecting at least two" specified devices. This functional language could support a broader interpretation covering any conductive structure or set of structures performing this role in the specified location.
    • Evidence for a Narrower Interpretation: The patent abstract refers to "a first first-layer contact" (singular), and the claim requires this contact to be "physically isolated from additional contacts in the upper portion of the ILD." (’757 Patent, Abstract; col. 12:60-63). This language, combined with figures that may depict a single, L-shaped conductor, could support a narrower construction requiring a single, monolithic structure.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges both induced and contributory infringement. Inducement is based on allegations that Intel provides its customers and foundry partners with Process Design Kits (PDKs), technical support, and instructive materials that encourage and direct the use of the allegedly infringing fabrication processes. (Compl. ¶¶104-107, 119-122). Contributory infringement is alleged on the basis that the accused processors are a material part of downstream products and have "no substantial non-infringing uses." (Compl. ¶¶111, 126).
  • Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for this allegation is that Intel has had "express and actual knowledge" of the patents and the alleged infringement no later than the date of the complaint's filing. (Compl. ¶¶112-113, 127-128).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of structural inherency versus implementation: Can MOSAID demonstrate that Intel's standard design rules and PDKs for its advanced process nodes necessarily and inherently result in the specific physical layouts claimed across the eleven asserted patents? Conversely, Intel may argue that its actual manufactured products contain structural or functional differences that place them outside the scope of the claims.
  • A key question of claim scope will turn on the construction of critical terms. For the ’957 patent, the case may hinge on the breadth of "substantially the same" in the context of nanoscale manufacturing tolerances. For the ’757 patent and others, a core issue will be whether claim terms like "first first-layer contact" require a single, monolithic structure as depicted in embodiments, or can be construed more broadly to cover functionally similar but structurally different interconnect schemes used in the accused devices.