DCT
1:25-cv-00834
Intellectual Ventures I LLC v. Lenovo Group Ltd
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Intellectual Ventures I LLC and Intellectual Ventures II LLC (Delaware)
- Defendant: Lenovo Group Limited (China)
- Plaintiff’s Counsel: Sorey & Hoover, LLP; Prince Lobel Tye LLP
- Case Identification: 1:25-cv-00834, W.D. Tex., 06/02/2025
- Venue Allegations: Plaintiff alleges venue is proper because a substantial part of the infringing acts occur within the district and Defendant is a foreign entity.
- Core Dispute: Plaintiff alleges that Defendant’s computers, smartphones, and tablets infringe six patents related to processor virtualization, high-speed memory calibration, and various wireless communication protocols.
- Technical Context: The asserted patents cover fundamental technologies in modern electronics, from processor-level context switching and memory signal timing to standardized protocols in Wi-Fi and cellular communications.
- Key Procedural History: The complaint alleges that several asserted patents originated from Transmeta Corporation, which successfully litigated a patent portfolio against Intel in 2006-2007. The complaint also alleges Defendant had pre-suit knowledge of several patents-in-suit based on prior litigation and specific communications from Plaintiff to Defendant dating back to 2022.
Case Timeline
| Date | Event |
|---|---|
| 2000-01-01 | Transmeta launches its first product, the Crusoe processor |
| 2000-11-07 | Transmeta initial public offering |
| 2003-10-01 | Transmeta launches its second processor, the Efficeon |
| 2003-11-17 | Earliest priority date for U.S. Patent No. 7,646,835 |
| 2004-05-20 | Earliest priority date for U.S. Patent No. 7,623,439 |
| 2005-03-31 | Earliest priority date for U.S. Patent No. 8,522,253 |
| 2006-01-25 | Earliest priority date for U.S. Patent No. 8,594,122 |
| 2006-05-02 | Earliest priority date for U.S. Patent No. 11,363,564 |
| 2006-08-11 | Earliest priority date for U.S. Patent No. 11,700,544 |
| 2006-10-01 | Transmeta sues Intel Corporation for patent infringement |
| 2007-10-01 | Transmeta and Intel settle litigation |
| 2009-02-01 | Intellectual Ventures acquires asserted patents originating from Transmeta |
| 2009-11-24 | U.S. Patent No. 7,623,439 issues |
| 2010-01-12 | U.S. Patent No. 7,646,835 issues |
| 2013-08-27 | U.S. Patent No. 8,522,253 issues |
| 2013-11-26 | U.S. Patent No. 8,594,122 issues |
| 2022-01-01 | Plaintiff alleges Defendant had knowledge of the ’564 patent via a claim chart |
| 2022-06-14 | U.S. Patent No. 11,363,564 issues |
| 2022-08-09 | Plaintiff alleges sending a presentation to Defendant identifying the ’122 patent |
| 2022-10-01 | Plaintiff alleges sending a presentation to Defendant identifying the ’253 patent |
| 2023-02-01 | Plaintiff alleges sending a presentation to Defendant identifying infringement of the ’253 patent |
| 2023-07-11 | U.S. Patent No. 11,700,544 issues |
| 2025-06-02 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,522,253 - "HARDWARE SUPPORT FOR VIRTUAL MACHINE AND OPERATING SYSTEM CONTEXT SWITCHING IN TRANSLATION LOOKASIDE BUFFERS AND VIRTUALLY TAGGED CACHES," issued August 27, 2013
The Invention Explained
- Problem Addressed: In computer systems running virtual machines (VMs), switching between different software processes ("context switching") or different VMs ("world switching") was inefficient because it required the system to flush its Translation Lookaside Buffer (TLB), a high-speed memory cache for address translations. These frequent flushes were computationally expensive and degraded performance (Compl. ¶¶ 15-16).
- The Patented Solution: The invention proposes a method to reduce these flushes by tagging each entry in the TLB with two separate identifiers: a first ID for the specific software process and a second ID for the VM in which it is running (’253 Patent, col. 2:50-59). This allows TLB entries for multiple processes across multiple VMs to coexist, so the entire TLB does not need to be flushed during every context or world switch (Compl. ¶17).
- Technical Importance: This approach was designed to improve the efficiency of computer systems using virtualization by minimizing the performance penalty associated with switching between different virtualized environments (Compl. ¶17).
Key Claims at a Glance
- The complaint asserts independent claim 5 (Compl. ¶78).
- The essential elements of claim 5 are:
- storing a first context ID and a second context ID in at least one entry of a translation lookaside buffer (TLB);
- storing a virtual address tag in the entries; and
- searching the TLB, which comprises:
- comparing the first context ID of an entry with a first provided context ID;
- comparing the second context ID of the entry with a second provided context ID;
- setting a match signal if at least one of the first or second comparisons indicates a match;
- comparing the virtual address tag of the entry with a provided virtual address tag; and
- generating a third match signal.
U.S. Patent No. 7,646,835 - "METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE," issued January 12, 2010
The Invention Explained
- Problem Addressed: High-speed memory systems, such as DDR2, rely on precise timing synchronization between different types of signals (e.g., command, data, and sampling signals). Factors like temperature, manufacturing variations, and aging can cause these signals to drift out of synchronization, leading to data errors and performance loss (Compl. ¶¶ 22-24).
- The Patented Solution: The patent describes a method for a memory controller to automatically calibrate these timing relationships. The system systematically alters the phase shifts of the command, data, and sampling signals to identify a "valid operation range" where the memory can function reliably (’835 Patent, Abstract). This calibration can be performed throughout the life of the memory to account for changing operating conditions (Compl. ¶25).
- Technical Importance: Automatic calibration is critical for achieving the high-speed and error-free operation required by modern memory standards such as LPDDR4 and LPDDR5 (Compl. ¶25).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶98).
- The essential elements of claim 1 are:
- A method for automatically calibrating timing relationships between command, data, and sampling signals, comprising:
- generating command signals to access an integrated circuit component;
- accessing data signals to convey data for the component;
- accessing sampling signals to control sampling of the data signals; and
- systematically altering a phase shift of the command signals, data signals, and sampling signals to determine a valid operation range that includes an optimal operation point.
- A method for automatically calibrating timing relationships between command, data, and sampling signals, comprising:
U.S. Patent No. 7,623,439 - "CYCLIC DIVERSITY SYSTEMS AND METHODS," issued November 24, 2009
- Technology Synopsis: The patent addresses a problem in OFDM-based wireless systems using multiple antennas (MIMO), where diversity schemes that delay a signal can be confused by a receiver with natural multipath delays (Compl. ¶32). The invention proposes using "cyclic advancement" rather than delay, which involves shifting a portion of a symbol's data into its preceding guard interval, making the artificially created diversity distinct from multipath delay and improving reception reliability (Compl. ¶33).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶121).
- Accused Features: The complaint alleges that wireless products supporting IEEE 802.11n, 802.11ac, and 802.11ax standards, which mandate a form of cyclic shift diversity, infringe the ’439 Patent (Compl. ¶121).
U.S. Patent No. 8,594,122 - "TRANSMIT ANNOUNCMENT INDICATION," issued November 26, 2013
- Technology Synopsis: The patent describes a method to reduce overhead in wireless communications, particularly for features like beamforming that require exchanging large amounts of information (Compl. ¶37). A transmitting device sends a first frame containing a "transmit announcement" that indicates a second frame will follow; this allows the second frame to be sent without the recipient's address, freeing up that space for other data. The second frame is sent after a short, defined interval (SIFS) to prevent interruption (Compl. ¶¶ 38-39).
- Asserted Claims: Independent claim 27 is asserted (Compl. ¶142).
- Accused Features: The complaint accuses products that support the IEEE 802.11ac VHT (Very High Throughput) Sounding Protocol, which allegedly uses the claimed transmit announcement method (Compl. ¶142).
U.S. Patent No. 11,700,544 - "COMMUNICATING OVER MULTIPLE RADIO ACCESS TECHNOLOGIES (RAT)," issued July 11, 2023
- Technology Synopsis: The patent addresses the high bandwidth demands of services like video streaming by enabling a mobile device to use two different radio access technologies (RATs), such as 4G/LTE and 5G, simultaneously for a single data download (Compl. ¶43). This differs from conventional systems where a second RAT serves only as a fallback. The invention proposes using the same protocol and security keys for both connections to minimize overhead (Compl. ¶43).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶161).
- Accused Features: The complaint accuses smartphones, such as the Motorola moto g 5G, that include chipsets featuring "dual simultaneous connectivity" using 4G/LTE and 5G RATs (Compl. ¶¶ 44, 161).
U.S. Patent No. 11,363,564 - "PAGING IN A WIRELESS NETWORK," issued June 14, 2022
- Technology Synopsis: The invention seeks to improve the efficiency of the "paging" procedure used by cellular networks to wake a mobile device from sleep mode (Compl. ¶45). Instead of sending both a brief paging indicator and the full, larger paging message on the same, potentially slow control channel, the invention uses a two-channel approach. The indicator on the control channel directs the device to a separate, high-bandwidth shared channel to receive the full paging message, leading to faster connection establishment (Compl. ¶47).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶187).
- Accused Features: The complaint accuses devices configured to support 3GPP LTE and/or 5G NR, such as the Motorola Razr+, which are alleged to use the claimed two-stage paging procedure (Compl. ¶48, 187).
III. The Accused Instrumentality
Product Identification
- For the ’253 Patent, the accused products are devices containing ARM Cortex-A78 based processors, such as the Motorola Razr+ 2024 smartphone (Compl. ¶78).
- For the ’835 Patent, the accused products are devices containing Qualcomm-based processors and LPDDR4, LPDDR4X, LPDDR5, or LPDDR5X memory, including the Lenovo Yoga Slim 7x and ThinkPad T14s Gen 6 laptops (Compl. ¶98).
Functionality and Market Context
- The functionality accused of infringing the ’253 Patent resides in the Memory Management Unit (MMU) of the ARM processors. The complaint alleges that the processor's Translation Lookaside Buffer (TLB) uses both an Address Space Identifier (ASID) to identify a process and a Virtual Machine Identifier (VMID) to identify a virtual machine, thereby enabling the claimed method of context switching without flushing the TLB (Compl. ¶¶ 80, 82-83).
- The functionality accused of infringing the ’835 Patent is the automatic memory "training" process performed by the Qualcomm processors to calibrate timing for the LPDDR memory. The complaint alleges this functionality is mandated by the JEDEC industry standard for LPDDR5X memory and involves systematically adjusting the phase of command (CA), data (DQ), and sampling (WCK) signals during device initialization to ensure reliable operation at high speeds (Compl. ¶¶ 101, 107).
IV. Analysis of Infringement Allegations
’253 Patent Infringement Allegations
| Claim Element (from Independent Claim 5) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| storing a first context ID and a second context ID in at least one entry of entries in a translation lookaside buffer (TLB) | Each TLB entry in the accused ARM processors stores a particular Address Space Identifier (“ASID”) and a particular Virtual Machine Identifier (“VMID”). | ¶80 | col. 2:52-54 |
| storing a virtual address tag in the entries | Each TLB entry includes a Virtual Address (“VA”) tag. | ¶81 | col. 2:48-49 |
| searching the TLB, wherein said searching comprises: comparing a first context ID of an entry with a first provided context ID and generating a first match signal | A TLB lookup compares the current ASID with the ASID stored in the TLB entry. | ¶82 | col. 3:1-3 |
| comparing a second context ID of the entry with a second provided context ID and generating a second match signal | A TLB lookup compares the current VMID with the VMID stored in the TLB entry. | ¶83 | col. 3:4-6 |
| setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match | A match signal is set to a match state under various conditions, such as when both the ASID and VMID match for certain requests. The complaint provides an image from an ARM technical manual describing the TLB match process (Compl. p. 31). | ¶84 | col. 3:7-10 |
| comparing the virtual address tag of the entry with a provided virtual address tag; and generating a third match signal | The Memory Management Unit compares the requested virtual address with the virtual address tag present in the TLB entry. | ¶85 | col. 3:11-13 |
Identified Points of Contention
- Scope Questions: A central question may be whether the ARM architecture's "ASID" and "VMID" correspond to the claimed "first context ID" and "second context ID," respectively. The defense may argue for a narrower construction based on the patent's specific embodiments.
- Technical Questions: Claim 5 recites setting a match state if "at least one" of the context ID comparisons match, which suggests OR logic. The complaint's factual allegation for this element describes a scenario where "if the first match signal with respect to the ASID and the second match signal with respect to the VMID indicate a match, the match signal is set to a match state" (Compl. ¶84). This apparent use of AND logic in the accused product's operation raises the question of whether it meets the claim's "at least one" (OR logic) requirement.
’835 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| generating command signals to access an integrated circuit component | The accused products use command/address (CA) signals to access LPDDR5X memory, as specified by the JEDEC standard. The complaint includes a table from the JEDEC standard defining command, data, and clock signals (Compl. p. 50). | ¶102 | col. 4:51-53 |
| accessing data signals to convey data for the integrated circuit component | The products use a bi-directional data (DQ) bus to convey data for the LPDDR5X memory. | ¶103 | col. 4:54-55 |
| accessing sampling signals to control sampling of the data signals | The products utilize WCK2CK Leveling, which uses sampling signals (WCK) to control the sampling of data signals. | ¶104 | col. 4:56-57 |
| systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range... | The accused products perform LPDDR5X signal "training" during initialization, which includes command bus training, WCK2CK Leveling, and WCK-DQ training to adjust the phase of all three signal types and establish a valid operating range. | ¶107 | col. 4:58-63 |
Identified Points of Contention
- Scope Questions: The construction of "systematically altering" may be a key issue. The complaint's evidence focuses on a "training" procedure that occurs at device initialization (Compl. ¶101). The defense may argue that the patent, which discusses accounting for variations "throughout the life" of the memory (Compl. ¶25), requires an ongoing or periodic calibration process, not just a one-time, power-on setup.
- Technical Questions: The claim requires altering all three signal types to "determine" a valid range. A question for the court will be what evidence shows that the accused JEDEC-compliant training procedures perform this three-part alteration for the specific purpose of determining a valid range, as opposed to simply setting predefined timing parameters.
V. Key Claim Terms for Construction
For the ’253 Patent
- The Term:
if at least one of the first match signal or the second match signal indicates a match - Context and Importance: This phrase defines the logical condition for a partial match based on context identifiers. Its construction is critical because the complaint alleges infringement based on an architecture that, in its primary operating mode, appears to require both identifiers to match. Practitioners may focus on this term because it creates a potential mismatch between the claim's OR logic and the accused product's alleged AND logic.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain language "at least one" strongly suggests OR logic. The patent's goal is to avoid unnecessary TLB flushes, which could be supported by allowing a match on just the VM-ID in certain circumstances, even if the process-ID differs.
- Evidence for a Narrower Interpretation: The specification describes a primary use case where, on a "world switch, both the first context and second context ID fields must match" (’253 Patent, col. 2:57-59). A defendant could argue this context limits the "at least one" language to specific, secondary situations not present in the accused functionality, or that the claim is invalid as indefinite if its logic is ambiguous.
For the ’835 Patent
- The Term:
systematically altering - Context and Importance: This term's scope will define whether a one-time initialization process infringes a claim that may be read to imply an ongoing, dynamic calibration. The dispute will likely center on whether "systematically altering" describes a single, comprehensive procedure or a recurring action.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term "systematically" on its own implies a methodical process, which would cover the structured training procedure described in the complaint (Compl. ¶107). The patent abstract does not contain an explicit temporal limitation requiring repeated alteration.
- Evidence for a Narrower Interpretation: The background of the invention explains the need to address timing variations that occur "over time" due to factors like aging and temperature changes (Compl. ¶24). This language may support an argument that "systematically altering" must be a process that can be performed "throughout the life of high-speed memory" (Compl. ¶25), not just once at startup.
VI. Other Allegations
- Indirect Infringement: The complaint alleges both induced and contributory infringement for the asserted patents. Inducement allegations are based on Defendant's advertisements, user manuals, and technical documentation for products containing ARM processors, Qualcomm chipsets, or supporting JEDEC and IEEE standards, which allegedly instruct end-users on how to use the infringing functionality (Compl. ¶¶ 87, 109). Contributory infringement is alleged based on the sale of components (e.g., ARM SoCs, Qualcomm processors) that are a material part of the inventions and are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶¶ 88, 110).
- Willful Infringement: The complaint alleges willful infringement for all asserted patents. The basis for willfulness includes alleged pre-suit knowledge from specific communications, such as PowerPoint presentations and claim charts sent by Plaintiff to Defendant in 2022 and 2023, and from Defendant's awareness of prior litigation involving the same or related patents (Compl. ¶¶ 89, 111, 131, 152, 200).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue for the ’253 patent will be one of logical scope: does the claim language requiring a match if "at least one" context ID is found (OR logic) read on the accused ARM architecture, which the complaint's own evidence suggests requires a match of both the process identifier (ASID) and virtual machine identifier (VMID) in its primary operational mode?
- For the ’835 patent and others tied to industry standards, a key question will be one of temporal application: can the patent term "systematically altering," described in the context of addressing performance degradation "over time," be construed to cover a one-time "training" or initialization procedure performed at device startup as mandated by standards like JEDEC?
- Across the portfolio, the case raises a fundamental question of infringement by standardization: does Lenovo's incorporation of third-party, standards-compliant components (e.g., ARM processors, Qualcomm modems, JEDEC-compliant memory controllers) that autonomously perform the claimed methods constitute direct infringement, and what level of knowledge and intent is required to prove indirect infringement based on the sale of such products?