DCT

1:25-cv-00834

Intellectual Ventures I LLC v. Lenovo Group Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00834, W.D. Tex., 06/02/2025
  • Venue Allegations: Venue is asserted based on Defendant being a foreign entity and on allegations that a substantial part of the infringing acts occur within the district, which includes a distribution facility in Laredo, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s computers, tablets, and smartphones infringe six patents related to processor virtualization, memory timing calibration, and various wireless communication technologies, including OFDM signal processing, beamforming protocols, multi-RAT connectivity, and cellular paging procedures.
  • Technical Context: The patents-in-suit cover a range of foundational technologies for modern electronic devices, addressing efficiency and performance in CPU virtualization, high-speed memory operation, and wireless communications compliant with 802.11 and 3GPP cellular standards.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of five of the six asserted patents, citing specific dates on which Plaintiff provided PowerPoint presentations, claim charts, or notice through prior litigation involving some of the same patents. The complaint also notes that two of the asserted patents originated at Transmeta Corporation, which previously litigated patents from its portfolio against Intel Corporation.

Case Timeline

Date Event
2003-11-17 Filing Date for U.S. Patent No. 7,646,835
2004-05-20 Priority Date for U.S. Patent No. 7,623,439
2005-03-31 Priority Date for U.S. Patent No. 8,522,253
2006-01-25 Priority Date for U.S. Patent No. 8,594,122
2006-05-02 Priority Date for U.S. Patent No. 11,363,564
2006-08-11 Priority Date for U.S. Patent No. 11,700,544
2009-11-24 U.S. Patent No. 7,623,439 Issued
2010-01-12 U.S. Patent No. 7,646,835 Issued
2013-08-27 U.S. Patent No. 8,522,253 Issued
2013-11-26 U.S. Patent No. 8,594,122 Issued
2022-06-14 U.S. Patent No. 11,363,564 Issued
2022-09-06 Qualcomm Snapdragon 6 Gen 1 announced
2023-07-11 U.S. Patent No. 11,700,544 Issued
2025-06-02 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,522,253 - "HARDWARE SUPPORT FOR VIRTUAL MACHINE AND OPERATING SYSTEM CONTEXT SWITCHING IN TRANSLATION LOOKASIDE BUFFERS AND VIRTUALLY TAGGED CACHES," Issued August 27, 2013

The Invention Explained

  • Problem Addressed: The complaint describes that in computers supporting virtual machines (VMs), switching between different software processes ("context switching") or different VMs ("world switching") required the computer to flush its translation lookaside buffer (TLB), a high-speed cache for memory addresses. These frequent and computationally expensive TLB flushes created performance inefficiencies (Compl. ¶¶ 15-16).
  • The Patented Solution: The invention proposes a method for reducing these flushes by adding more specific identifiers to each entry in the TLB. As described in the patent, the context-ID register is extended to have two fields: a "per-process context-ID field" and a "virtual machine context-ID field" (’253 Patent, col. 5:29-37; Compl. ¶75). This allows entries for multiple processes and multiple VMs to coexist in the same TLB, enabling the processor to invalidate entries on a more granular, per-process scale without flushing entries belonging to other VMs (Compl. ¶¶ 17, 75).
  • Technical Importance: This approach aimed to improve the performance of virtualized computing environments by reducing the overhead associated with managing memory address translations during context and world switches (Compl. ¶17).

Key Claims at a Glance

  • The complaint asserts independent method Claim 5 (Compl. ¶78).
  • Claim 5 requires, in part:
    • storing a first context ID and a second context ID in at least one entry of a TLB;
    • storing a virtual address tag in the entries; and
    • searching the TLB by comparing the first and second context IDs with provided IDs, setting a match signal if at least one of them matches, and then comparing the virtual address tag.

U.S. Patent No. 7,646,835 - "METHOD AND SYSTEM FOR AUTOMATICALLY CALIBRATING INTRA-CYCLE TIMING RELATIONSHIPS FOR SAMPLING SIGNALS FOR AN INTEGRATED CIRCUIT DEVICE," Issued January 12, 2010

The Invention Explained

  • Problem Addressed: High-speed memory systems, such as those using the DDR2 standard, depend on the precise synchronization of command, data, and sampling signals. The complaint notes that environmental factors like temperature changes and electromagnetic interference, as well as component aging, can cause these signals to lose synchronization, leading to data errors and performance loss (Compl. ¶¶ 24, 94).
  • The Patented Solution: The patent describes a method for a memory controller to automatically calibrate these critical timing relationships. The system systematically alters the phase shift of the command (CA), data (DQ), and sampling (DQS) signals to identify a "valid operation range" where the memory can operate reliably and to find an "optimal operation point" within that range (’835 Patent, Abstract; Compl. ¶¶ 25, 55). This automatic calibration allows the system to adapt to changing operating conditions over the life of the device (Compl. ¶25).
  • Technical Importance: This automated approach was designed to improve the reliability and maximum performance of computer systems using high-speed memory, relaxing the strict design tolerances that were previously required (Compl. ¶¶ 25, 95).

Key Claims at a Glance

  • The complaint asserts independent method Claim 1 (Compl. ¶98).
  • Claim 1 requires, in part:
    • A method for automatically calibrating timing relationships between command, data, and sampling signals.
    • The method includes generating command signals, accessing data signals, and accessing sampling signals.
    • It further requires "systematically altering a phase shift" of all three signal types "to determine a valid operation range" for the device, which includes an "optimal operation point."

U.S. Patent No. 7,623,439 - "CYCLIC DIVERSITY SYSTEMS AND METHODS," Issued November 24, 2009

  • Technology Synopsis: The patent addresses an issue in OFDM-based wireless systems where diversity schemes using "cyclic delay" could be misinterpreted by a receiver as a multipath delay from the environment (Compl. ¶32). The invention proposes using "cyclic advancement," which shifts a portion of the symbol data forward into the guard interval, to create a temporal decorrelation that is distinguishable from multipath effects, thereby improving signal acquisition and reducing errors (Compl. ¶¶ 33, 117-118).
  • Asserted Claims: At least Claim 1 (Compl. ¶121).
  • Accused Features: The complaint alleges infringement by wireless products supporting IEEE 802.11n/ac/ax standards, which allegedly mandate a "cyclic diversity shift" feature when transmitting OFDM packets. Accused products include the Lenovo ThinkPad T14s Gen 6, Legion Tab Gen 3, and Motorola Razr+ 2024 (Compl. ¶121).

U.S. Patent No. 8,594,122 - "TRANSMIT ANNOUNCMENT INDICATION," Issued November 26, 2013

  • Technology Synopsis: To improve wireless network efficiency, particularly for overhead-intensive features like beamforming, the invention describes a method where a first communication frame includes a "transmit announcement indication." This indication notifies the receiver that a second frame will follow, which allows the second frame to be sent without the recipient's address, thereby reducing overhead. The second frame is transmitted after a Short Inter-Frame Space (SIFS) to prevent interruption (Compl. ¶¶ 37-39, 136-137).
  • Asserted Claims: At least Claim 27 (Compl. ¶142).
  • Accused Features: The complaint accuses products that support the IEEE 802.11ac standard's Very High Throughput (VHT) Sounding Protocol for beamforming, alleging this protocol implements the patented announcement method. The Lenovo Yoga Tab Plus is identified as an exemplary accused product (Compl. ¶¶ 142, 144).

U.S. Patent No. 11,700,544 - "COMMUNICATING OVER MULTIPLE RADIO ACCESS TECHNOLOGIES (RAT)," Issued July 11, 2023

  • Technology Synopsis: The patent addresses the demand for higher bandwidth by enabling a user device to use two different radio access technologies (e.g., 4G/LTE and 5G) simultaneously to receive a single stream of multimedia data, rather than using one as a fallback (Compl. ¶¶ 43, 158). The system is designed to minimize overhead by using the same packet data protocol and security keys for both simultaneous connections (Compl. ¶¶ 43, 159).
  • Asserted Claims: At least Claim 1 (Compl. ¶161).
  • Accused Features: The complaint targets user devices, such as the Motorola moto g Stylus 5G smartphone, that include chipsets featuring "dual simultaneous connectivity" using 4G/LTE and 5G RATs, as defined in 3GPP standards for Multi-Radio Dual Connectivity (MR-DC) (Compl. ¶¶ 44, 164).

U.S. Patent No. 11,363,564 - "PAGING IN A WIRELESS NETWORK," Issued June 14, 2022

  • Technology Synopsis: The invention improves the efficiency of waking a mobile device from sleep mode ("paging"). Conventionally, a small paging indicator and a larger paging message were sent on the same, often low-bandwidth, control channel. The patented method separates these onto two channels: the device monitors a control channel for the indicator, which then directs it to a separate, shared transport channel optimized for larger data, where the full paging message is received. This leads to faster connection and better battery efficiency (Compl. ¶¶ 47, 184).
  • Asserted Claims: At least Claim 1 (Compl. ¶187).
  • Accused Features: The complaint accuses devices configured to support 3GPP LTE and/or 5G NR standards, such as the Motorola Razr+. It alleges that the paging procedures defined in these standards, which separate the paging indicator (on PDCCH) from the paging message (on PDSCH), practice the claimed invention (Compl. ¶¶ 48, 192-194).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses a broad range of Lenovo's products, including computers, desktops, tablets, smartphones, and laptops (Compl. ¶78). Specific examples cited across the various counts include the Motorola Razr+ 2024, Motorola Moto G Stylus 5G, Lenovo Yoga Slim 7x, Lenovo ThinkPad T14s Gen 6, Legion Tab Gen 3, and Lenovo Yoga Tab Plus (Compl. ¶¶ 78, 98, 121, 142, 161, 187).

Functionality and Market Context

  • The allegations focus on core technological components and standards-based functionalities within these devices.
    • For the ’253 Patent, the accused functionality is the hardware support for virtualization in ARM Cortex-A78 based processors, which allegedly use Address Space Identifiers (ASID) and Virtual Machine Identifiers (VMID) to manage TLB entries (Compl. ¶¶ 78, 80).
    • For the ’835 Patent, the functionality is the automatic memory "training" process in Qualcomm-based processors that control LPDDR4/5/5X memory, which is required by the JEDEC industry standard (Compl. ¶¶ 98-99). The complaint provides a screenshot of a Qualcomm Snapdragon 6 Gen 1 processor, identifying it as an 8-core chipset announced on September 6, 2022 (Compl. p. 30).
    • For the remaining patents, the accused functionalities are tied to compliance with wireless standards: IEEE 802.11n/ac/ax for cyclic diversity and transmit announcements, and 3GPP standards for 4G/LTE and 5G for multi-RAT connectivity and paging procedures (Compl. ¶¶ 121, 142, 163, 189).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,522,253 Infringement Allegations

Claim Element (from Independent Claim 5) Alleged Infringing Functionality Complaint Citation Patent Citation
storing a first context ID and a second context ID in at least one entry of entries in a translation lookaside buffer (TLB); The accused ARM processors store an Address Space Identifier ("ASID") and a Virtual Machine Identifier ("VMID") in each TLB entry. ¶80 col. 5:29-37
storing a virtual address tag in the entries; Each TLB entry in the accused processors includes a Virtual Address ("VA") tag. ¶81 col. 2:38-40
comparing a first context ID of an entry with a first provided context ID and generating a first match signal; A TLB lookup in the accused processor compares the current ASID with the ASID stored in the TLB entry. ¶82 col. 6:22-25
comparing a second context ID of the entry with a second provided context ID and generating a second match signal; A TLB lookup in the accused processor compares the current VMID with the VMID stored in the TLB entry. ¶83 col. 6:26-28
setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match; A match is set under several conditions, including if an entry is marked 'global' and the VMID matches, or if a request originates from a secure state and the ASID matches. ¶84 col. 6:32-35
comparing the virtual address tag of the entry with a provided virtual address tag; and generating a third match signal. The processor's Memory Management Unit (MMU) compares the requested virtual address with the virtual address present in the TLB entry to determine a match. ¶85 col. 6:38-41
  • Identified Points of Contention:
    • Scope Questions: A central question may be whether the "Address Space Identifier (ASID)" and "Virtual Machine Identifier (VMID)" used in the accused ARM architecture correspond in scope and function to the claimed "first context ID" and "second context ID," respectively. The complaint alleges a direct mapping (Compl. ¶80).
    • Technical Questions: Claim 5 requires setting a match if "at least one" of the context ID comparisons indicates a match. The complaint's evidence describes a more complex logic in the ARM architecture where, for some operations, both ASID and VMID must match (Compl. ¶84). The analysis will question whether the accused product's combination of logical conditions (which includes scenarios where only one ID is needed) satisfies the claim's "at least one" (disjunctive OR) requirement. A screenshot from an Arm technical manual illustrates the conditions for a TLB match, which include scenarios where "The ASID matches" and "The VMID matches" (Compl. p. 38).

U.S. Patent No. 7,646,835 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
generating command signals to access an integrated circuit component; The accused products use command/address (CA) signals, as specified by the JEDEC LPDDR5X standard, to access the memory component. ¶102 col. 3:15-18
accessing data signals to convey data for the integrated circuit component; The accused products use a bi-directional data bus (DQ signals) to convey data to and from the LPDDR5X memory. ¶103 col. 3:19-25
accessing sampling signals to control sampling of the data signals; The accused products utilize "WCK2CK Leveling," which uses WCK clock signals to control the sampling of the DQ data signals. ¶104 col. 3:26-29
systematically altering a phase shift of the command signals, a phase shift of the data signals, and a phase shift of the sampling signals to determine a valid operation range... The accused products perform mandatory "training" procedures during initialization, including Command Bus training (altering command signal phase), WCK-DQ training (altering data signal phase), and WCK2CK Leveling (altering sampling signal phase), to establish critical timing relationships for reliable operation. ¶¶105-107 col. 4:14-20
  • Identified Points of Contention:
    • Scope Questions: The infringement theory hinges on whether the standardized, one-time "training" procedures for LPDDR memory (Compl. ¶101) meet the definition of "systematically altering ... to determine a valid operation range" as claimed. A screenshot of a JEDEC standard excerpt lists several training procedures, including "Command Bus Training," "Write Leveling," and "Write Training (DQS-DQ Training)" (Compl. p. 46).
    • Technical Questions: What evidence does the complaint provide that the accused "training" procedures do more than set the memory to a single pre-determined operating point? The claim requires "determin[ing] a valid operation range," which suggests an exploratory process that may be more extensive than a standard initialization routine.

V. Key Claim Terms for Construction

For U.S. Patent No. 8,522,253:

  • The Term: "setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match"
  • Context and Importance: This term defines the core logical operation for a context match. Its construction is critical because the accused ARM architecture employs a complex set of conditions for a match, which is not a simple OR operation in all cases (Compl. ¶84). Practitioners may focus on whether the accused product's logic, which includes AND conditions for standard operations, can ever satisfy this "at least one" (OR) requirement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification describes a scenario where only one ID matters: "If the TLB or cache entry has the global bit set..., the entry's context-ID field must match the machine-instantiation virtual machine ID field..." (’253 Patent, col. 6:32-35). This provides a specific example where a match is based on only the second context ID, which may support reading the "at least one" language to cover systems that use different logic for different situations.
    • Evidence for a Narrower Interpretation: The overall description of switching between virtual machines implies that both the process and the VM are relevant contexts. A defendant may argue that the primary inventive concept requires tracking both, and the "at least one" language should not be read to ignore the conjunctive logic used in the accused product's primary, non-global operating mode.

For U.S. Patent No. 7,646,835:

  • The Term: "systematically altering ... to determine a valid operation range"
  • Context and Importance: This phrase is central to the infringement analysis. The complaint equates standardized memory "training" with this claimed process (Compl. ¶101, 107). Practitioners may focus on this term because the defendant will likely argue that a one-time initialization routine is not the same as the exploratory, range-finding process described in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not require the process to be continuous or to occur during runtime; a methodical, one-time procedure at startup could be considered "systematic." The claim's ultimate goal is to find an "optimal operation point," which is the goal of a training routine (’835 Patent, cl. 1).
    • Evidence for a Narrower Interpretation: The specification includes pseudo-code for searching a multi-dimensional "configuration space" to "find the valid region of operation" and "precisely identify the boundaries" (’835 Patent, col. 6:1-25, col. 5:48-50). This language suggests a more comprehensive, boundary-defining search than what a standard training protocol might perform.

VI. Other Allegations

  • Indirect Infringement: For all six patents, the complaint alleges active inducement by providing products to customers and instructing them on how to use the infringing features (e.g., via user manuals and marketing materials that promote compliance with the relevant standards) (Compl. ¶¶ 87, 109, 129, 150, 177, 198). Contributory infringement is also alleged, based on providing key components (e.g., ARM-based SoCs, Wi-Fi chipsets) that are a material part of the invention and not suitable for substantial non-infringing use (Compl. ¶¶ 88, 110, 130, 151, 180, 199).
  • Willful Infringement: The complaint alleges willful infringement for all patents. For the ’253, ’835, ’439, ’122, and ’564 patents, it alleges pre-suit knowledge based on specific communications (PowerPoint presentations, claim charts) or notice via prior litigation (Compl. ¶¶ 89, 111, 131, 152, 200). For the ’544 patent, willfulness is based on knowledge "since at least when it received a copy of this Complaint" (Compl. ¶178).

VII. Analyst’s Conclusion: Key Questions for the Case

This case presents a multi-front challenge to core technologies in modern electronic devices. The dispute will likely focus on the following central questions:

  • A primary issue will be one of standards equivalence: For each asserted patent, can the functionality mandated by widely adopted industry standards (e.g., ARM architecture, JEDEC memory standards, IEEE 802.11, 3GPP cellular standards) be construed to meet the specific limitations recited in the patent claims? This raises the question of whether implementing a standard necessarily equates to practicing the patented invention.
  • A key evidentiary question will be one of functional operation: Does the accused functionality, as implemented, perform the specific steps required by the claims? For example, does the complex matching logic in an ARM processor satisfy the ’253 patent’s "at least one" requirement, and does a standardized memory "training" routine perform the exploratory, range-determining process claimed by the ’835 patent?
  • A third question will concern knowledge and intent: Given the allegations of pre-suit notice for five of the six patents, the litigation may heavily scrutinize what Defendant knew about the patents and when, which will be central to the claims for willful and indirect infringement.