1:25-cv-01228
Empire Technology Development LLC v. NVIDIA Corp
I. Executive Summary and Procedural Information
Parties & Counsel:
- Plaintiff: Empire Technology Development LLC (Delaware)
- Defendant: NVIDIA Corporation (Delaware) and NVIDIA Singapore Pte. Ltd. (Singapore)
- Plaintiff’s Counsel: The Dacus Firm, P.C.; Erise IP, PA.
Case Identification: 1:25-cv-01228, W.D. Tex., 08/06/2025
Venue Allegations: Venue is alleged to be proper as to NVIDIA Corporation based on its regular and established place of business in Austin, Texas. For NVIDIA Singapore Pte. Ltd., venue is based on its status as a foreign defendant, which may be sued in any judicial district.
Core Dispute: Plaintiff alleges that Defendant’s NVIDIA Grace CPUs, and products incorporating them, infringe a patent related to methods for congestion-aware data routing in computer interconnection networks.
Technical Context: The technology addresses data traffic bottlenecks in complex, multi-nodal processors by using both local and non-local network status information to make more intelligent routing decisions, a key challenge in high-performance computing and artificial intelligence systems.
Key Procedural History: The patent-in-suit originated from research at the University of Texas. The complaint notes that one of the named inventors, Dr. Stephen W. Keckler, is currently employed by Defendant NVIDIA as the head of its Architecture Research Group. Plaintiff, Empire Technology Development LLC, is the exclusive licensee of the patent with the right to sue for infringement.
Case Timeline
| Date | Event |
|---|---|
| 2007-01-01 (Approx.) | Inventors at the University of Texas began research. |
| 2008-08-26 | Exclusive license agreement granted to Plaintiff's predecessor. |
| 2009-02-17 | Earliest Patent Priority Date (U.S. App. No. 12/372,556). |
| 2014-04-08 | U.S. Patent No. 8,694,704 Issues. |
| 2023-01-01 (Approx.) | NVIDIA releases the first Accused Products. |
| 2025-08-06 | Complaint filed. |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,694,704 - "METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK"
The Invention Explained
- Problem Addressed: The patent describes a problem in on-chip networks where data routing is inefficient. Some systems use fixed paths, making them "oblivious" to network congestion. Other "adaptive" systems react to congestion, but typically only based on local information, such as the status of a router and its immediate neighbors, which is insufficient to avoid larger, regional traffic jams in complex processors (’704 Patent, col. 3:22-44).
- The Patented Solution: The invention proposes a system where routers make decisions using both local congestion data and non-local status information propagated from distant, indirectly-coupled routers. An "aggregation unit" within a router combines these local and non-local metrics to create a more comprehensive view of network traffic, allowing data packets to be routed around congested regions rather than just immediate bottlenecks (’704 Patent, Abstract; col. 7:22-31; Fig. 3).
- Technical Importance: This method of regional congestion awareness was designed to improve load balancing and reduce latency, enabling greater efficiency and performance in the increasingly complex multi-processor chips required for high-performance computing (Compl. ¶2).
Key Claims at a Glance
- The complaint asserts independent apparatus claim 10 (Compl. ¶56).
- The essential elements of independent claim 10 are:
- A multi-nodal processor with a network-on-chip comprising a first node, a second node, and a third node, each with processor units and output channels.
- The second node includes a router device.
- The third node is coupled to the first and second nodes and includes a local status unit (to provide local congestion information) and an aggregation unit.
- The aggregation unit is configured to combine non-local status information (from the first node) with its own local status information to produce a first aggregate status information.
- The second node is configured to route data based on this first aggregate status information received from the third node.
- The complaint reserves the right to assert additional claims (Compl. ¶54).
III. The Accused Instrumentality
Product Identification
The complaint identifies the NVIDIA Grace CPU and products containing it, such as the NVIDIA GH200 Grace Hopper Superchip and NVIDIA Grace Blackwell Superchips, as the "Accused Products" (Compl. ¶¶8, 57).
Functionality and Market Context
- The accused NVIDIA Grace CPU is a multi-nodal processor designed for high-performance AI and data center applications (Compl. ¶¶40, 51). It features a proprietary "NVIDIA Scalable Coherency Fabric" (SCF), which the complaint alleges is a network-on-chip that functions as the claimed interconnection network (Compl. ¶¶58, 67).
- The complaint alleges that the Grace CPU implements a congestion management feature known as "CBusy" (Completer Busy) to regulate data traffic. This feature, which the complaint alleges is based on Arm's CMN-700 mesh network technology, allegedly provides the local and non-local status information used for routing decisions, as required by the patent (Compl. ¶¶62, 67-69). A screenshot from Arm materials describes the CBusy feature as providing "automatic regulation of CPU request traffic based on system congestion" (Compl. ¶22).
- The Accused Products are positioned as critical components for the AI industry, with NVIDIA's CEO quoted as stating they are designed to be "extraordinarily performant in a power-limited environment" (Compl. ¶4).
IV. Analysis of Infringement Allegations
’704 Patent Infringement Allegations
| Claim Element (from Independent Claim 10) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first node of a network-on-chip of a multinodal processor, the first node comprising a first plurality of output channels... and a first processor unit... | The complaint maps the "first node" to a section of the NVIDIA Grace CPU's network-on-chip architecture, identifying its processor cores and output channels. An annotated diagram identifies this node within the chip's fabric (Compl. ¶18). | ¶58 | col. 18:50-54 |
| a second node of the network-on-chip... the second node... comprising a router device configured to route the second data; | The "second node" is mapped to another section of the Grace CPU, which is alleged to contain a router device. The complaint provides an annotated diagram highlighting this component (Compl. ¶20). | ¶59 | col. 18:55-61 |
| a third node of the network-on-chip... the third node... comprising... a local status unit configured to provide first local status information regarding congestion... | The "third node" is mapped to a further section of the Grace CPU architecture. Its "local status unit" is alleged to be a "Scalable Coherency Fabric Cache Slice Controller" (SCC), which is equivalent to a "Home Node" that provides a "CBusy" indication of local congestion. | ¶¶60, 66, 68 | col. 19:2-5 |
| an aggregation unit configured to combine the non-local status information corresponding to the first node and the first local status information to produce first aggregate status information... | The "aggregation unit" is alleged to be the "Home Node" (or SCC) in the third node, which receives a CBusy indication from another node and "propagates" a combined value to a requesting node. | ¶69 | col. 19:6-10 |
| wherein the second node is configured to route second data based on the first aggregate status information. | The complaint alleges that a "Request Node/Core" in the "second node" receives the CBusy indication (the aggregate status) and uses it to choose a routing path for subsequent data requests, either to the busy subordinate node or to a different one. | ¶71 | col. 19:14-16 |
Identified Points of Contention
- Scope Questions: A central dispute may be whether the accused "CBusy" feature, described as a mechanism for "regulation to CPU traffic" (Compl. ¶22), meets the claim requirement of providing "status information regarding congestion." The patent describes congestion in terms of specific metrics like virtual channel counts and crossbar demand (’704 Patent, col. 6:17-34), raising the question of whether NVIDIA's more general traffic throttling system falls within the patent's scope.
- Technical Questions: The complaint alleges that the "Home Node" functions as the claimed "aggregation unit" by receiving and propagating a CBusy value (Compl. ¶69). A key technical question will be whether this act of "propagating" a signal is functionally equivalent to "combining" local and non-local information to "produce" a new "aggregate status information" as required by the claim language. The complaint's own annotated diagram highlights a feature for "HN-F to SN-F CBusy based throttling" (Compl. ¶29), and the court will need to determine if this alleged throttling mechanism performs the combination and routing functions recited in the claim.
V. Key Claim Terms for Construction
The Term: "aggregation unit"
- Context and Importance: This term is central to the invention's novelty, as it describes the component that creates the "regionally-aware" congestion metric. The infringement case depends on whether the accused "Home Node" in the NVIDIA Grace CPU, which allegedly receives and propagates a "CBusy" signal (Compl. ¶69), performs the function of an "aggregation unit".
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent states the aggregation unit is "configured to combine" non-local and local information (’704 Patent, col. 19:6-8). A party could argue that "combine" should be read broadly to include any logical process that uses multiple information inputs to generate a guiding output, not necessarily a strict mathematical calculation.
- Evidence for a Narrower Interpretation: The specification provides a specific example where the aggregation unit determines the "arithmetic mean" of weighted inputs using an "add function" and a "right-shift function" (’704 Patent, col. 7:50-col. 8:2). A party could argue this disclosure limits the term to a component that performs a mathematical combination, not one that merely forwards or prioritizes signals.
The Term: "local status information regarding congestion"
- Context and Importance: The infringement theory hinges on equating NVIDIA's "CBusy" signal with the patent's concept of "local status information regarding congestion". Practitioners may focus on this term because the defense will likely argue that "CBusy" is a different type of performance-management signal.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent’s background broadly frames the problem as network "congestion" causing slowdowns (’704 Patent, col. 3:22-30). The term could be construed to cover any metric indicating network "busyness." The complaint alleges CBusy is based on "system congestion" (Compl. ¶22).
- Evidence for a Narrower Interpretation: The specification discloses specific examples of congestion metrics, including a "count of free virtual channels" and a "crossbar demand metric" (’704 Patent, col. 6:17-34). A party could argue these examples limit the term to metrics that directly measure the availability of specific hardware routing resources, as opposed to a higher-level system utilization or traffic throttling signal like CBusy.
VI. Other Allegations
Indirect Infringement
The complaint alleges induced infringement, stating that NVIDIA provides customers with "instructive materials, technical support, and information concerning the operation and use of the Accused Products" that allegedly guide users to operate the Grace CPUs in an infringing manner (Compl. ¶77).
Willful Infringement
Willfulness is alleged based on NVIDIA's purported knowledge of the ’704 Patent. The complaint asserts this knowledge arises from the fact that one of the patent's named inventors, Dr. Keckler, is a Vice President at NVIDIA, heading its Architecture Research group. This allegation suggests NVIDIA had knowledge of the invention from at least the patent's issue date in 2014, and was therefore aware of or willfully blind to its infringement (Compl. ¶¶78, 82).
VII. Analyst’s Conclusion: Key Questions for the Case
A core issue will be one of definitional scope and technical mapping: can the term "congestion", which the patent describes with specific network-level metrics like virtual channel counts, be construed to cover the accused "CBusy" feature, which is presented as a system-level traffic regulation or throttling mechanism? The outcome will depend on both claim construction and evidence of how the accused system technically operates.
A second key question will be one of functional equivalence: does the accused architecture perform the specific functions recited in Claim 10? For example, does the accused "aggregation unit" (the "Home Node") merely propagate a status signal, or does it actively "combine" local and non-local information to "produce" a new "aggregate status information" that is then used to "route" data, as strictly required by the claim language?
Finally, the allegation that a named inventor is a senior employee at NVIDIA raises a significant question of willful infringement. The case will likely examine what knowledge of the patented invention can be imputed to the corporation and whether NVIDIA's actions following that potential knowledge were objectively reckless.