DCT
1:25-cv-01228
Empire Technology Development LLC v. NVIDIA Corp
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Empire Technology Development LLC (Delaware)
- Defendant: NVIDIA Corporation (Delaware) and NVIDIA Singapore Pte. Ltd. (Singapore)
- Plaintiff’s Counsel: The Dacus Firm, P.C.; Erise IP, PA.
- Case Identification: 1:25-cv-01228, W.D. Tex., 08/06/2025
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because NVIDIA Corporation maintains a regular and established place of business in Austin and has committed acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s NVIDIA Grace CPUs and products containing them infringe a patent related to congestion-aware routing techniques in computer interconnection networks.
- Technical Context: The technology addresses data traffic management within complex, multi-nodal processors, a critical function for improving performance and efficiency in high-performance computing, particularly for modern AI and data center applications.
- Key Procedural History: The complaint notes that one of the patent’s inventors, Dr. Stephen Keckler, is currently employed by Defendant NVIDIA as the head of its Architecture Research Group. Plaintiff is the exclusive licensee of the patent-in-suit from the University of Texas System.
Case Timeline
| Date | Event |
|---|---|
| 2009-02-17 | ’704 Patent Priority Date |
| 2014-04-08 | ’704 Patent Issue Date |
| 2023-Q1 | Accused Product (NVIDIA Grace CPU) First Release |
| 2025-08-06 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 8,694,704, "METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK," issued April 8, 2014 (’704 Patent).
The Invention Explained
- Problem Addressed: In multi-nodal processing, data packets must be efficiently routed between numerous processing nodes on a chip. The patent’s background section states that prior routing methods were often either oblivious to network congestion or relied solely on "local congestion information," such as conditions at an immediately adjacent router, which could lead to inefficient load balancing and bottlenecks in complex networks (’704 Patent, col. 3:22-44).
- The Patented Solution: The invention describes a system where routers in a network-on-chip make routing decisions based on a combination of local congestion status and "non-local" status information received from other, non-adjacent routers in the network (’704 Patent, col. 4:46-59). An "aggregation unit" within a router combines these local and non-local metrics to generate an "aggregate status," which provides a more comprehensive view of network traffic, allowing data to be routed more intelligently around congested areas (’704 Patent, Fig. 3; col. 7:22-40).
- Technical Importance: This approach of propagating and aggregating congestion information from beyond a router's immediate neighbors was designed to improve overall throughput and performance in increasingly complex multi-processor systems (Compl. ¶¶ 47-48).
Key Claims at a Glance
- The complaint asserts infringement of at least independent claim 10 (Compl. ¶56).
- Independent Claim 10 is an apparatus claim directed to a network-on-chip with at least three nodes, with essential elements including:
- A first node and a second node that are "indirectly coupled" to each other.
- A third node that is directly coupled to both the first and second nodes, serving as the intermediary.
- The third node contains a "local status unit" to provide local congestion information.
- The third node also contains an "aggregation unit" configured to combine its own local status information with "non-local status information" received from the first node to produce a "first aggregate status information."
- The third node provides this aggregate status information to the second node.
- The second node is configured to route its data based on the received aggregate status information.
III. The Accused Instrumentality
Product Identification
- The accused products are NVIDIA Grace CPUs and all products containing them, including the NVIDIA GH200 Grace Hopper Superchip, NVIDIA Grace Blackwell Superchips, and various datacenter products like the NVIDIA GB200 NVL72 and cloud services like NVIDIA DGX Cloud (Compl. ¶8). A marketing image from NVIDIA's website is provided to identify the accused product line (Compl. ¶57).
Functionality and Market Context
- The complaint alleges the NVIDIA Grace CPU is a multi-nodal processor designed for high-performance AI and data center applications (Compl. ¶¶ 4, 40). Its relevant technical feature is the NVIDIA Scalable Coherency Fabric (SCF), described as a "mesh fabric and distributed cache architecture" that connects the CPU's 72 Arm Neoverse V2 cores and other components (Compl. ¶¶ 61, 67). The complaint alleges this SCF implements congestion-aware techniques, such as a feature referred to as "CBusy," to manage data flow and avoid bottlenecks between the cores, cache, and memory (Compl. ¶¶ 62, 66). These features are alleged to be critical to the performance that makes the Grace CPUs important for the AI sector (Compl. ¶48).
IV. Analysis of Infringement Allegations
’704 Patent Infringement Allegations
| Claim Element (from Independent Claim 10) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first node of a network-on-chip of a multinodal processor... | The NVIDIA Grace CPU contains a first node, identified in an annotated diagram as a processor core and associated components within the chip's fabric. | ¶58 | col. 4:9-12 |
| a second node of the network-on-chip... the second node further comprising a router device... | The Grace CPU contains a second node, identified as another processor core with a router, also within the chip's fabric. | ¶59 | col. 4:9-12 |
| wherein the first node is indirectly coupled to the second node via the third node | The first and second nodes are not directly connected but are communicatively coupled through the third node. | ¶63 | col. 4:55-59 |
| a third node of the network-on-chip... the third node coupled directly to the first node... and... directly coupled to the second node... | The Grace CPU contains a third node, identified as another processor core, which is directly connected to both the first and second nodes within the SCF. An annotated diagram shows these direct connections (Compl. ¶60). | ¶60 | col. 18:58-62 |
| the third node... comprising... a local status unit configured to provide first local status information regarding congestion... | The third node includes a component (identified as a "transaction completer node" or "Home Node") that provides a "CBusy indication or other indication of local status regarding congestion." | ¶66 | col. 7:11-21 |
| an aggregation unit configured to combine the non-local status information corresponding to the first node and the first local status information to produce first aggregate status information... | The third node's Home Node allegedly receives a CBusy indication from a subordinate node and "propagate[s]" it, thereby combining local and non-local status to produce an aggregate status value. | ¶69 | col. 7:22-35 |
| wherein the second node is configured to route second data based on the first aggregate status information. | The second node (a Request Node/Core) is informed of the busyness of other nodes via the CBusy indication and can choose to route subsequent requests to a different node based on that information. | ¶71 | col. 8:5-9 |
- Identified Points of Contention:
- Scope Questions: A central dispute may arise over whether the architectural components of the NVIDIA Grace CPU map onto the claimed "nodes." The complaint alleges that processor cores and associated cache units within the Scalable Coherency Fabric function as the claimed "first," "second," and "third" nodes. The case may turn on whether the term "node" as defined and used in the ’704 Patent can be construed to read on these specific microarchitectural elements.
- Technical Questions: The complaint's infringement theory relies heavily on the functionality of a feature called "CBusy" to meet the "local status unit" and "aggregation unit" limitations. A key technical question will be whether the CBusy mechanism, which provides "regulation to CPU traffic based on system congestion" (Compl. ¶62), performs the specific combination of local and non-local status information to produce an aggregate status, as required by the claim, or if it operates in a technically distinct manner.
V. Key Claim Terms for Construction
The Term: "aggregation unit"
- Context and Importance: This term is central to the invention, as it describes the core logic for combining different types of congestion data. The infringement case hinges on whether the accused Grace CPU contains a structure that performs this claimed function. Practitioners may focus on this term because the complaint maps it to the alleged propagation of "CBusy" signals within the accused device's "Home Node" (Compl. ¶69).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Claim 10 itself defines the term functionally as a unit "configured to combine the non-local status information... and the first local status information to produce first aggregate status information" (’704 Patent, col. 19:5-10). This functional language may support a construction that is not limited to a specific hardware implementation.
- Evidence for a Narrower Interpretation: The specification discloses specific embodiments of the aggregation unit, for example, one that determines an "arithmetic mean" of weighted inputs using an "add function 405" and a "right-shift function 411" (’704 Patent, col. 8:46-51; Fig. 4). A defendant might argue that the term's scope should be limited by these more detailed examples.
The Term: "node"
- Context and Importance: The entire structure of claim 10 is built on a specific relationship between a "first node," "second node," and "third node." The validity of the plaintiff's infringement theory depends on successfully mapping these claimed nodes to components within the NVIDIA Grace CPU, such as individual processor cores or cache controllers (Compl. ¶¶ 58-60).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes a "multinodal processor" as having a "processing node array" that can include any number of "processing nodes," which in turn contain a "data processing unit" (’704 Patent, col. 4:9-15, 50). This general description could support a broad interpretation covering various sub-components of a modern CPU.
- Evidence for a Narrower Interpretation: The patent figures, such as Figure 2, depict the nodes (104) as distinct, tiled blocks in a grid-like array, each coupled to its neighbors via clear communication channels. This could support an argument that a "node" must be a discrete, self-contained processing block, potentially narrower than the complaint's application of the term to interconnected cores within a coherent fabric.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement by asserting that NVIDIA provides customers and end-users with "instructive materials, technical support, and information concerning the operation and use of the Accused Products" that encourage infringing use (Compl. ¶77). It also alleges contributory infringement, stating that the accused products are "especially made or especially adapted to practice the invention" and are not staple articles of commerce (Compl. ¶80).
- Willful Infringement: Willfulness is alleged based on pre-suit knowledge of the ’704 Patent. The complaint asserts that NVIDIA had knowledge "since at least its issue date (April 4, 2014)" due to its employment of Dr. Keckler, one of the patent's named inventors (Compl. ¶78). Knowledge is also alleged from the filing of the complaint itself (Compl. ¶78).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural mapping: can the patent’s conceptual three-node structure, defined by terms like "node", "aggregation unit", and "indirectly coupled", be persuasively mapped onto the physical and logical reality of the NVIDIA Grace CPU's complex Scalable Coherency Fabric and its associated cores and caches?
- A central evidentiary question will be one of functional operation: does NVIDIA's "CBusy" congestion-notification mechanism perform the specific two-part function required by Claim 10—combining distinct local status with propagated non-local status to create an aggregate value used for routing—or is there a fundamental mismatch in its technical operation compared to what the patent claims?
- The dispute over willfulness will likely raise a key legal question regarding imputed knowledge: under what circumstances can an inventor's knowledge of a patent be legally imputed to their corporate employer to establish the knowledge and intent required for willful infringement, particularly when the employment began after the invention was conceived?