DCT

1:25-cv-01320

HD Silicon Solutions LLC v. NXP Semiconductors NV

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01320, W.D. Tex., 08/19/2025
  • Venue Allegations: Venue is based on Defendants maintaining regular and established places of business in the Western District of Texas, including U.S. corporate headquarters, a design and manufacturing facility, and a Smart Home Innovation Lab in Austin.
  • Core Dispute: Plaintiff alleges that Defendant’s various processors and microcontrollers infringe six patents related to semiconductor fabrication processes, secure debug access, and processor power management.
  • Technical Context: The patents address distinct technical challenges in modern semiconductors: creating reliable electrical connections on-chip, securing chip-level debug interfaces against unauthorized access, and reducing power consumption in low-power states.
  • Key Procedural History: Two of the asserted patents have recently survived Inter Partes Review (IPR) proceedings. U.S. Patent No. 7,810,002 had numerous claims invalidated, but the asserted claims 10 and 13 were found to remain valid and enforceable. U.S. Patent No. 6,774,033 also had numerous claims invalidated, with the asserted claim 8 being the sole surviving claim following an appeal to the Federal Circuit. This history significantly narrows the scope of the dispute for these patents to the specific language of the surviving claims.

Case Timeline

Date Event
2000-10-23 ’731 and ’264 Patents Priority Date
2002-11-04 ’033 Patent Priority Date
2004-08-10 U.S. Patent No. 6,774,033 Issued
2005-06-28 ’002 and ’166 Patents Priority Date
2005-09-29 ’173 Patent Priority Date
2007-08-21 U.S. Patent No. 7,260,731 Issued
2008-02-19 U.S. Patent No. 7,334,173 Issued
2009-10-06 U.S. Patent No. 7,600,166 Issued
2010-10-05 U.S. Patent No. 7,810,002 Issued
2016-09-06 U.S. Patent No. 9,436,264 Issued
2020-11-22 ’731 Patent Expired
2020-12-06 ’264 Patent Expired
2022-11-04 ’033 Patent Expired
2022-11-07 Final Written Decision in IPR for ’033 Patent
2023-04-04 Final Written Decision in IPR for ’002 Patent
2025-02-06 Federal Circuit affirms IPR decision for ’033 Patent
2025-06-28 ’002 Patent Expired
2025-08-19 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,810,002 - "Providing Trusted Access to a JTAG Scan Interface in a Microprocessor"

The Invention Explained

  • Problem Addressed: The patent describes a security risk posed by standard processor debug interfaces like the Joint Test Action Group (JTAG) scan chain. These interfaces provide low-level access to a chip's internal states, which can be exploited to discover processor-specific secrets or compromise sensitive operations (Compl. ¶1; ’002 Patent, col. 1:21-34).
  • The Patented Solution: The invention proposes securing this access through a trusted software layer. By default, the JTAG interface is disabled. To gain access, an external entity must send an authentication message to a trusted software layer running on the processor. This software layer verifies the message (e.g., by checking a cryptographic signature) and, if valid, enables the JTAG interface, typically by setting a specific internal hardware register (’002 Patent, col. 5:10-54, FIG. 5).
  • Technical Importance: This approach provides a mechanism to secure powerful but inherently insecure hardware debug tools, a critical function for processors intended to handle secure and trusted data (’002 Patent, col. 1:31-34).

Key Claims at a Glance

  • The complaint asserts independent claim 11 (via dependent claim 13) and alleges claims 10 and 13 are valid and enforceable (Compl. ¶¶18, 37, 74).
  • Independent Claim 11 requires a system comprising:
    • A secure processor
    • A JTAG scan interface coupled to the processor
    • A trusted software communicatively coupled to the processor for validating an authentication message
    • A communication buffer for receiving the authentication message
    • An authentication link directly coupling the buffer to the trusted software
    • An internal register for enabling the JTAG interface when set
  • The complaint reserves the right to assert additional claims (Compl. ¶74).

U.S. Patent No. 6,774,033 - "Metal Stack for Local Interconnect Layer"

The Invention Explained

  • Problem Addressed: In semiconductor manufacturing, using a single layer of titanium nitride for local on-chip wiring can cause "resist poisoning," where the nitrogen reacts with and degrades the photoresist used for patterning. A conventional solution—oxidizing the titanium nitride surface—creates a hard, high-resistance layer that makes subsequent electrical testing difficult (’033 Patent, col. 2:23-48).
  • The Patented Solution: The invention teaches a composite "metal stack" for the interconnect layer. A first film of titanium nitride is deposited on an oxide layer, followed by a second film of tungsten. The tungsten top layer is chemically stable, preventing resist poisoning, while the underlying titanium nitride acts as an effective etch stop for patterning the tungsten, improving process control (’033 Patent, Abstract; col. 4:36-41).
  • Technical Importance: This two-film structure offers a method to form reliable local interconnects that avoids the competing problems of resist poisoning and high contact resistance, leading to a more robust manufacturing process (’033 Patent, col. 4:36-59).

Key Claims at a Glance

  • The complaint asserts claim 8, which survived an IPR and subsequent Federal Circuit appeal (Compl. ¶¶22, 79).
  • Claim 8 depends on claim 1 and adds a key functional limitation. The combined elements require:
    • A method of forming a local interconnect layer by depositing a first film of titanium nitride over an oxide layer
    • Depositing a second film of tungsten over the first film
    • Wherein the resulting two-film "metal stack" has a sheet resistance equal to or less than about 10 Ohm/sq
  • The complaint reserves the right to proceed under the doctrine of equivalents (Compl. ¶79).

U.S. Patent No. 7,600,166 - "Method and System for Providing Trusted Access to a JTAG Scan Interface in a Microprocessor"

  • Technology Synopsis: This patent is from the same family as the ’002 patent and addresses the same technical problem: securing a processor’s JTAG debug interface from unauthorized access. The solution similarly involves using a trusted software layer to authenticate a received message before enabling the otherwise-disabled JTAG interface (Compl. ¶23).
  • Asserted Claims: At least claim 11 (Compl. ¶¶37, 84).
  • Accused Features: The accused features are the secure debug functionalities of various NXP processors and microcontrollers, which allegedly use a challenge/response protocol managed by a software layer to grant access to a debug interface via an internal register (Compl. ¶¶38, 40, 42, 44, 46, 48, 51, 53, 55, 57, 59, 61).

U.S. Patent No. 7,334,173 - "Method and System for Protecting Processor from Unauthorized Debug Access"

  • Technology Synopsis: This patent addresses securing a scan test architecture by performing an authentication operation to authorize the use of a protected scan chain. It describes disabling a protected scan chain by default and enabling it only after a successful authentication, which can involve comparing a control scan chain's elements against secret key values (Compl. ¶26).
  • Asserted Claims: At least claim 31 (Compl. ¶¶37, 89).
  • Accused Features: The accused features are the secure debug functionalities across numerous NXP product families, which allegedly employ authentication protocols and challenge/response mechanisms to control access to a restricted JTAG interface (Compl. ¶¶38, 40, 42, 44, 46, 48, 51, 53, 55, 57, 59, 61).

U.S. Patent No. 9,436,264 - "Saving Power when in or Transitioning to a Static Mode of a Processor"

  • Technology Synopsis: This patent describes a method for reducing processor power consumption when transitioning to a low-power "static mode" where the system clock is disabled. The method involves reducing the processor's core voltage to a level sufficient to maintain memory state but insufficient for processing activity, and transitioning a voltage regulator between different regulation modes to manage the voltage change efficiently (Compl. ¶29).
  • Asserted Claims: At least claim 1 (Compl. ¶¶62, 64, 94).
  • Accused Features: The accused features are the internal power management capabilities of the S32K1 and Kinetis families of microcontrollers. These products allegedly provide multiple power options, allowing a transition from a computing mode to a reduced operation mode where the system clock is disabled and core voltage is adjusted to maintain memory state (Compl. ¶¶63, 65).

U.S. Patent No. 7,260,731 - "Saving Power when in or Transitioning to a Static Mode of a Processor"

  • Technology Synopsis: This patent is from the same family as the ’264 patent and addresses the same technical problem of reducing power during a processor's static or "deep sleep" mode. The solution involves reducing the core voltage to a value sufficient to maintain state while the system clock is disabled (Compl. ¶33).
  • Asserted Claims: At least claim 1 (Compl. ¶¶62, 64, 99).
  • Accused Features: The accused features are the power management functions of the S32K1 and Kinetis microcontroller families, which allegedly can transition to a reduced operation mode by disabling the system clock and adjusting core voltage to maintain state but not processing activity (Compl. ¶¶63, 65).

III. The Accused Instrumentality

Product Identification

The complaint names a wide array of NXP semiconductor products, including the i.MX Series, VFxxx Series, S32G2, S32V2, S32R294, and Layerscape processors, as well as the LPC55S6x, LPC55S2x, LPC55S1x, i.MX-RT, S32K1, and Kinetis families of microcontrollers (Compl. ¶¶37-69).

Functionality and Market Context

The complaint targets three distinct functionalities across these product families:

  1. Secure Debug Access: The majority of the accused products are alleged to infringe the ’002, ’166, and ’173 patents. The complaint alleges these products implement a secure debug mode, often using a Serial Wire Debug (SWD) interface controlled by a Secure JTAG Controller (SJC). Access is allegedly restricted via a software-managed challenge/response authentication protocol that, upon success, sets an internal register to grant access to the debug interface (Compl. ¶¶38, 40, 53).
  2. Power Management: The S32K1 and Kinetis families of microcontrollers are accused of infringing the ’264 and ’731 patents. These products allegedly include internal power management features that allow them to transition from a normal computing mode to a reduced-power mode (e.g., "Very Low Power Stop") in which the system clock is disabled and the core voltage is lowered to a level sufficient to maintain memory state but not processing activity (Compl. ¶¶63, 65).
  3. Interconnect Fabrication: The S32G2, Layerscape LX2160A, and S32R294 processors, which utilize 16-nm FinFET process technology, are accused of infringing the ’033 patent. The complaint alleges these processors are fabricated with a local interconnect layer comprising a titanium nitride film deposited on an oxide layer, followed by a tungsten film, with the resulting metal stack having a sheet resistance of 10 Ohm/sq or less (Compl. ¶¶49, 67, 69).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

’002 Patent Infringement Allegations

Claim Element (from Independent Claim 11 of parent ’166 Patent) Alleged Infringing Functionality Complaint Citation Patent Citation
a secure processor; The accused products (e.g., i.MX8 Series) are alleged to comprise a "secure processor" with trusted resources (Compl. ¶38). ¶38 col. 10:17-21
a JTAG scan interface coupled to said secure processor... The accused products utilize a debug interface, such as a Serial Wire Debug (SWD) or a Secure JTAG Controller (SJC), to access processor functions (Compl. ¶38). ¶38 col. 10:17-21
a trusted software communicatively coupled to said secure processor for validating an authentication message... The accused products allegedly use a software layer to manage a challenge/response protocol, which serves as the authentication mechanism before granting access (Compl. ¶38). ¶38 col. 10:22-26
a communication buffer for receiving said authentication message... The complaint does not provide sufficient detail for analysis of this specific element, but implies such a function by describing the receipt and processing of authentication information (Compl. ¶38). ¶38 col. 10:27-33
a register internal to said secure processor for enabling said JTAG scan interface when properly set... The complaint alleges that upon successful authentication, "an internal register within the secure processor is set," which in turn enables access to the JTAG interface via an "enable switch, coupled to this internal register" (Compl. ¶38). ¶38 col. 10:37-43

Identified Points of Contention

  • Scope Questions: A primary question may be whether the term "JTAG scan interface," as used in the patent, can be construed to cover the "Serial Wire Debug (SWD)" interface that the complaint alleges "replaces the traditional JTAG interface" in the accused products (Compl. ¶38). The analysis may turn on whether SWD is merely a different implementation of a JTAG-compliant interface or a distinct technology outside the patent's scope.
  • Technical Questions: The complaint alleges a "software layer" performs authentication (Compl. ¶38). A point of contention could be whether this software layer meets the "trusted software" limitation of the claim, which the patent describes as having authorized access to trusted resources within the secure processor (’166 Patent, col. 11:35-40).

’033 Patent Infringement Allegations

Claim Element (from Claim 8) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of forming a local interconnect layer... comprising: depositing a first film over an oxide layer, the first film comprising titanium nitride; and The accused S32G2 processors allegedly comprise a local interconnect layer "made by depositing a first film comprising titanium nitride over an oxide layer" (Compl. ¶49). ¶49 col. 6:55-57
depositing a second film over the first film, the second film comprising tungsten... The accused processors allegedly have "A second film comprising tungsten... deposited over the first film" (Compl. ¶49). ¶49 col. 7:1-3
wherein the first film and the second film form a metal stack having a sheet resistance equal to or less than about 10 Ohm/sq. The complaint alleges these film layers "form a metal stack of the local interconnect layer having a sheet resistance of 10 Ohm/sq or less" (Compl. ¶49). ¶49 col. 7:23-26

Identified Points of Contention

  • Evidentiary Questions: The complaint’s infringement theory for the ’033 patent directly mirrors the language of claim 8. The central dispute will likely be factual and evidentiary: does the fabrication process for the accused 16-nm FinFET processors actually involve the claimed two-layer titanium nitride/tungsten stack for the local interconnect, and does that structure in the final product meet the specific sheet resistance requirement of 10 Ohm/sq or less?

V. Key Claim Terms for Construction

For the ’002 and ’166 Patents:

  • The Term: "JTAG scan interface"
  • Context and Importance: This term is central because the complaint accuses products that allegedly use a "Serial Wire Debug (SWD)" interface that "replaces the traditional JTAG interface" (Compl. ¶38). The viability of the infringement claim depends on whether this term is construed narrowly to mean only an interface compliant with the specific IEEE 1149.1 (JTAG) standard, or more broadly to encompass other serial debug interfaces that perform similar functions.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's background describes the problem in terms of "support interfaces intended for debugging" generally, with JTAG being a prominent example, suggesting the invention's applicability may not be strictly limited to the JTAG standard itself (’166 Patent, col. 1:15-16).
    • Evidence for a Narrower Interpretation: The claims, abstract, and detailed description consistently and repeatedly refer specifically to "JTAG scan interface" without mentioning alternatives like SWD, which could support a construction limited to the well-defined industry standard known by that name (’166 Patent, Abstract; col. 11:17).

For the ’033 Patent:

  • The Term: "local interconnect layer"
  • Context and Importance: The definition of this term is critical for determining if the accused structures in modern FinFET processors fall within the patent's scope. Practitioners may focus on whether the term implies specific structural or functional limitations tied to the technology of the early 2000s when the patent was filed.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims themselves define the layer by its method of formation (a TiN film and a tungsten film over oxide) and its resulting electrical property (sheet resistance ≤ 10 Ohm/sq), without further structural limitations, suggesting any structure meeting these criteria could infringe (’033 Patent, col. 7:1-26).
    • Evidence for a Narrower Interpretation: The background section describes a "local interconnect layer" as being "typically formed under a first metal layer" and providing "relatively short electrical paths between devices within a cell" (’033 Patent, col. 1:28-32). This contextual description could be used to argue that the term is limited to such specific applications and does not cover all interconnects made with the claimed materials.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendants have been "actively and knowingly inducing purchasers and owners of Infringing Products" to infringe the Asserted Patents (Compl. ¶70). The Prayer for Relief requests a judgment that Defendants have "actively induced and contributed to infringement" (Prayer for Relief, ¶A).
  • Willful Infringement: The complaint does not contain an explicit allegation of willful infringement or plead facts related to pre-suit knowledge of the patents.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope: can the term "JTAG scan interface," used throughout patents filed in the mid-2000s, be construed to cover the modern "Serial Wire Debug (SWD)" interfaces that the complaint alleges are used in NXP's products? The outcome of this question will likely determine the viability of infringement claims for three of the six asserted patents.
  • A second central conflict appears to be one of factual verification: for the ’033 patent concerning semiconductor fabrication, the complaint’s allegations track the claim language with precision. The dispute will likely focus on technical evidence from discovery, answering whether NXP’s 16-nm FinFET manufacturing process actually creates the specific two-layer titanium-nitride/tungsten structure and whether that structure meets the claimed sheet-resistance threshold.
  • Finally, a key strategic question will be the impact of extensive IPR proceedings: with the two lead patents having been narrowed to a small subset of their original claims that have been confirmed as valid, the litigation is pre-focused on very specific technical features. This history may streamline claim construction but also raises the stakes for the infringement analysis, as there is less room for either party to maneuver on questions of claim scope and validity.