DCT

1:25-cv-01320

HD Silicon Solutions LLC v. NXP Semiconductors NV

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Key Events
Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01320, W.D. Tex., 12/23/2025
  • Venue Allegations: Venue is alleged to be proper based on Defendant’s regular and established places of business in the Western District of Texas, including its U.S. corporate headquarters, design facilities, and manufacturing facilities located in Austin, Texas.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor processors and microcontrollers infringe five patents related to semiconductor fabrication methods, processor power-saving techniques, and secure access to on-chip debug interfaces.
  • Technical Context: The patents-in-suit address fundamental technologies in modern semiconductor design: chip fabrication processes, power management for mobile and low-power devices, and security mechanisms for on-chip testing and debugging.
  • Key Procedural History: U.S. Patent No. 6,774,033 was the subject of an Inter Partes Review (IPR2021-00752), resulting in a final written decision finding claims 1-7 and 9-17 unpatentable. This decision was affirmed by the U.S. Court of Appeals for the Federal Circuit. The complaint asserts that only claim 8 of this patent remains valid and enforceable. Additionally, three of the five asserted patents ('033, '264, and '731) are expired, limiting potential damages to past infringement.

Case Timeline

Date Event
2000-10-23 Priority Date for ’731 and ’264 Patents
2002-11-04 Priority Date for ’033 Patent
2004-08-10 ’033 Patent Issued
2005-09-29 Priority Date for ’173 and ’166 Patents
2007-08-21 ’731 Patent Issued
2008-02-19 ’173 Patent Issued
2009-10-06 ’166 Patent Issued
2016-09-06 ’264 Patent Issued
2020-11-12 Asserted Patents Assigned to Plaintiff HDSS
2020-11-22 ’731 Patent Expired
2020-12-06 ’264 Patent Expired
2022-11-04 ’033 Patent Expired
2022-11-07 Final Written Decision in IPR for ’033 Patent
2025-02-06 Federal Circuit Affirms IPR Decision for ’033 Patent
2025-12-23 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,774,033 - "Metal Stack for Local Interconnect Layer"

The Invention Explained

  • Problem Addressed: The patent’s background section describes a problem in semiconductor fabrication known as "resist poisoning," where nitrogen from a titanium nitride film reacts with and degrades the photoresist material used for patterning, adversely affecting the process. An alternative solution, oxidizing the titanium nitride, creates a hard layer that makes electrical probing difficult and increases resistance (’033 Patent, col. 2:25-48).
  • The Patented Solution: The invention proposes a method for forming a local interconnect layer using a two-layer metal stack. A first film of titanium nitride is deposited onto an oxide layer, followed by a second film of tungsten deposited over the titanium nitride. The tungsten layer serves as a chemically stable cap, preventing resist poisoning and providing a reliable surface for electrical testing, while the titanium nitride acts as an adhesion layer and etch stop (’033 Patent, Abstract; col. 3:6-20).
  • Technical Importance: This approach provided a method to improve manufacturing yield for local interconnects by avoiding the resist poisoning issue without requiring an extra oxidation step, which introduced its own problems with electrical testing and resistance (’033 Patent, col. 3:46-59).

Key Claims at a Glance

  • The complaint asserts infringement of dependent claim 8, which depends from independent claim 1. Claim 1 was found unpatentable in an IPR proceeding (Compl. ¶13, 72).
  • Essential elements of underlying independent claim 1 include:
    • A method of forming a local interconnect layer in an integrated circuit, comprising:
    • depositing a first film over an oxide layer, the first film comprising titanium nitride; and
    • depositing a second film over the first film, the second film comprising tungsten, the first film and the second film forming a metal stack of the local interconnect layer.
  • Additional essential element of dependent claim 8:
    • wherein the first film and the second film form a metal stack having a sheet resistance equal to or less than about 10 Ohm/sq.

U.S. Patent No. 7,600,166 - "Method and System for Providing Trusted Access to a JTAG Scan Interface in a Microprocessor"

The Invention Explained

  • Problem Addressed: The patent addresses the security risk posed by standard on-chip debug interfaces, such as the Joint Test Action Group (JTAG) interface. These interfaces provide low-level access to a processor's internal states, which could be exploited after manufacturing to discover "processor specific secrets" or compromise sensitive operations (’166 Patent, col. 1:17-31).
  • The Patented Solution: The invention describes a system where the JTAG interface is disabled by default. A "trusted software layer" running on a "secure processor" acts as a gatekeeper. To enable the JTAG interface, an external tool must send an authentication message, which the trusted software validates. Only upon successful validation does the trusted software set an internal register to enable the JTAG interface (’166 Patent, Abstract; col. 2:5-14).
  • Technical Importance: This technology provides a way to secure debug interfaces after a product ships, allowing manufacturers to perform failure analysis while preventing unauthorized parties from using the same interface to compromise device security (’166 Patent, col. 1:26-31).

Key Claims at a Glance

  • The complaint asserts infringement of at least independent claim 11 (Compl. ¶28, 30, 32, 34, 36, 38, 41, 43, 45, 55, 57, 59).
  • Essential elements of independent claim 11 (a system claim) include:
    • a secure processor;
    • a JTAG scan interface coupled to the secure processor;
    • a trusted software communicatively coupled to the secure processor for validating an authentication message;
    • a communication buffer for receiving the authentication message;
    • an authentication link coupling the communication buffer to the trusted software; and
    • a register internal to the secure processor for enabling the JTAG scan interface when set by the trusted software.

U.S. Patent No. 7,334,173 - "Method and System for Protecting Processor from Unauthorized Debug Access"

  • Technology Synopsis: This patent, from the same family as the ’166 Patent, also addresses securing debug interfaces. It describes disabling a protected test chain by default and requiring an authentication operation where a "candidate value" (provided via an unprotected control scan chain) is compared against a stored "secret key value" to authorize use of the protected chain (’173 Patent, Abstract; col. 2:45-49).
  • Asserted Claims: At least claim 31 (Compl. ¶28, 30, 32, 34, 36, 38, 41, 43, 45, 55, 57, 59).
  • Accused Features: The accused products are alleged to use an Authentication Debug Module (ADM) and a Secure JTAG Controller (SJC) that function as an authentication logic, restricting JTAG access until a secret-key challenge/response protocol is successfully executed (Compl. ¶85).

U.S. Patent No. 9,436,264 - "Saving Power when in or Transitioning to a Static Mode of a Processor"

  • Technology Synopsis: This patent addresses power consumption when a processor is idle. It describes a method for transitioning a processor to a static or "deep sleep" mode, in which the system clock is disabled, by reducing the core voltage to a level sufficient to maintain the processor's state but not sufficient to maintain processing activity. The method also involves transitioning a voltage regulator between different regulation modes to save power during the voltage change (’264 Patent, Abstract; col. 2:4-10).
  • Asserted Claims: At least claim 1 (Compl. ¶61, 63).
  • Accused Features: The accused microcontrollers’ power management features are alleged to allow transitions to reduced operation modes where clocks are shut off and a voltage regulator reduces voltage to a level sufficient to maintain memory state (Compl. ¶62, 64, 90).

U.S. Patent No. 7,260,731 - "Saving Power when in or Transitioning to a Static Mode of a Processor"

  • Technology Synopsis: This patent is an earlier member of the same family as the ’264 Patent and addresses the same technical problem. It describes a method for reducing power by determining a processor is transitioning to a mode with a disabled system clock, reducing the core voltage with a voltage regulator to maintain state, and managing power dissipation during the transition to a power saving mode (’731 Patent, Abstract; col. 2:4-10).
  • Asserted Claims: At least claim 1 (Compl. ¶61, 63).
  • Accused Features: The complaint accuses the same power management features as for the ’264 Patent, namely the ability to enter low-power modes by disabling clocks and reducing core voltage via an on-chip voltage regulator (Compl. ¶62, 64, 95).

III. The Accused Instrumentality

Product Identification

  • A wide range of Defendant’s semiconductor products are accused, including the i.MX Series, VFxxx Series, S32 Series, and Layerscape processors, as well as the LPC, i.MX-RT, S32K1, and Kinetis families of microcontrollers (Compl. ¶¶ 28-68).

Functionality and Market Context

  • The complaint alleges that certain accused processors (S32G2, Layerscape LX2160A, S32R294) are manufactured using a 16-nm FinFET process that creates a local interconnect layer composed of a titanium nitride film and a tungsten film, resulting in low sheet resistance (Compl. ¶¶ 40, 66, 68).
  • A large number of the accused processor and microcontroller families are alleged to implement a secure JTAG debug interface. These products allegedly use components such as a Secure JTAG Controller (SJC) and an Authentication Debug Module (ADM) to enforce a challenge/response authentication protocol that must be passed before an internal register is set to grant access to the JTAG interface (Compl. ¶¶ 29, 31, 33, 35, 39, 85).
  • The S32K1 and Kinetis microcontroller families are alleged to include internal power management features allowing them to transition to low-power modes (e.g., Very Low Power Stop). This transition allegedly involves disabling the system clock, gating the core clock, and using a voltage regulator to reduce the core voltage to a level sufficient to maintain memory state but not to support processing activity (Compl. ¶¶ 62, 64).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'033 Patent Infringement Allegations

Claim Element (from Independent Claim 1, incorporated into Claim 8) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of forming a local interconnect layer... comprising: depositing a first film over an oxide layer, the first film comprising titanium nitride; The accused processors are alleged to comprise a local interconnect layer made by depositing a first film of titanium nitride over an oxide layer. ¶40, 66, 68 col. 2:63-65
and depositing a second film over the first film, the second film comprising tungsten... A second film comprising tungsten is alleged to be deposited over the first film. ¶40, 66, 68 col. 3:11-14
Additional element from Claim 8: wherein the first film and the second film form a metal stack having a sheet resistance equal to or less than about 10 Ohm/sq. The resulting film layers are alleged to form a metal stack with a sheet resistance of 10 Ohm/sq or less. ¶40, 66, 68 col. 6:23-26

Identified Points of Contention

  • Scope Questions: Infringement of a method claim requires performance of the claimed steps. A key question will be whether the complaint provides sufficient factual basis to allege that Defendant's manufacturing process for its 16-nm FinFET products performs the specific deposition steps recited in the claim.
  • Technical Questions: Given that independent claim 1 was found unpatentable, the case for claim 8 infringement will depend entirely on the "sheet resistance" limitation. The analysis may focus on whether this specific electrical property is a consistent and direct result of the accused manufacturing method for all accused products.

'166 Patent Infringement Allegations

Claim Element (from Independent Claim 11) Alleged Infringing Functionality Complaint Citation Patent Citation
a secure processor; Accused products are alleged to comprise a secure processor. ¶29, 31, 33 col. 2:38-39
a JTAG scan interface coupled to said secure processor... Accused products are alleged to utilize a JTAG interface for debugging and testing. ¶29 col. 2:39-40
a trusted software communicatively coupled to said secure processor for validating an authentication message... A "software layer" is alleged to be authorized to access trusted resources and verify authentication information before granting JTAG access. ¶29, 31, 33 col. 2:40-44
a communication buffer for receiving said authentication message... The i.MX8 processor's Authentication Debug Module (ADM) is alleged to serve as a communication buffer for authentication. ¶80 col. 3:28-30
a register internal to said secure processor for enabling said JTAG scan interface when properly set... An internal register is allegedly set within the secure processor to enable JTAG access after authentication is validated. ¶29, 31, 33 col. 3:35-38

Identified Points of Contention

  • Scope Questions: The analysis may raise the question of whether the accused "software layer" constitutes the "trusted software" as contemplated by the patent. The construction of "trusted software" will be critical, particularly regarding its required level of security, privilege, and isolation.
  • Technical Questions: A central question may be whether the accused hardware components, such as the Authentication Debug Module (ADM) and Secure JTAG Controller (SJC), map directly onto the claimed system architecture. For example, does the ADM function as a "communication buffer" for the "trusted software," or does it play a distinct role in a different security architecture?

V. Key Claim Terms for Construction

Patent: ’033 Patent

  • The Term: "a sheet resistance equal to or less than about 10 Ohm/sq" (from claim 8)
  • Context and Importance: This limitation is the sole element distinguishing the asserted valid claim 8 from the invalidated independent claim 1. Its interpretation is dispositive for infringement. Practitioners may focus on whether "about 10" provides any range and whether the property must be a direct result of the specific method recited in claim 1.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The use of the word "about" suggests the patentee did not intend a strict numerical limit. The patent specification itself shows test results with some variation (’033 Patent, Tables 1 & 2).
    • Evidence for a Narrower Interpretation: The patent presents a specific embodiment (300 Angstroms of tungsten over 300 Angstroms of titanium nitride) that achieves a sheet resistance of 9.41 Ohms/sq (’033 Patent, col. 5:15-19, Table 1). A defendant may argue that the claim is limited to results achieved through processes closely mirroring this specific, successful embodiment.

Patent: ’166 Patent

  • The Term: "trusted software" (from claim 11)
  • Context and Importance: The plaintiff's infringement theory relies on mapping the accused products' "software layer" to this claim term. The definition of what constitutes "trusted" will be a central point of contention.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification defines the term functionally as software that "has authorized access to trusted resources in the trusted processor" (’166 Patent, col. 2:40-42). This could be interpreted to cover any firmware or software with the necessary permissions, regardless of the specific security architecture.
    • Evidence for a Narrower Interpretation: The patent’s Figure 4 depicts the "trusted software layer" (405) as distinct from an "untrusted software layer" (403), suggesting an architecture with specific privilege separation. The complaint's reference to Arm Cortex architecture and "worlds" (Compl. ¶80) may lead a defendant to argue that "trusted software" implies a specific, highly privileged execution environment like that provided by ARM TrustZone, and that their accused "software layer" does not meet this requirement.

VI. Other Allegations

  • Indirect Infringement: The complaint states that the plaintiff "reserves the right to allege induced infringement claims" if evidence arises during discovery (Compl. p. 22, fn. 29). No specific facts supporting inducement are pleaded in the current complaint.
  • Willful Infringement: The complaint does not include allegations of willful infringement or pre-suit knowledge of the patents.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of validity and proof for the ’033 patent: Following the IPR that invalidated the parent claim, can the plaintiff prove that the defendant's standard manufacturing process not only performs the method of claim 1 but also necessarily and consistently achieves the specific "sheet resistance... less than about 10 Ohm/sq" required by the sole surviving dependent claim 8?
  • A key evidentiary question will be one of architectural equivalence for the ’166 and ’173 patents: Do the accused processors’ security components, such as the Secure JTAG Controller and Authentication Debug Module, functionally map onto the specific system elements recited in the claims (e.g., "trusted software," "communication buffer," "authentication logic"), or is there a fundamental mismatch in their technical architecture and operation?
  • A central question for the ’264 and ’731 patents will be one of functional scope: Do the accused microcontrollers' power management features perform the specific, claimed method steps for transitioning a processor and its voltage regulator into a power-saving mode, or do they achieve a similar result through a technically distinct process?