Mila US Inc v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mila US Inc (Texas)
  • Defendant: NVIDIA Corp (Delaware)
  • Plaintiff’s Counsel: BC LAW GROUP, Group
• Case Identification: 1:25-cv-01359, W.D. Tex., 09/25/2025
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Nvidia is registered to do business in Texas, has transacted business in the district, and maintains regular and established places of business within the district.
• Core Dispute: Plaintiff alleges that Defendant’s graphics processing units (GPUs), systems-on-chip (SoCs), and related processor architectures infringe six patents related to image and data processing, memory interfaces, system control, and error correction.
• Technical Context: The technologies at issue concern fundamental aspects of modern semiconductor design, including methods for efficiently processing graphics, managing data flow in parallel computing architectures, and ensuring system reliability.
• Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of infringement via letters dated December 3, 2024, and March 13, 2025. Uniquely, for U.S. Patent No. 8,275,975, the complaint alleges Defendant had notice as early as June 20, 2014, through a U.S. Patent and Trademark Office Non-Final Rejection issued against one of Defendant's own patent applications, which cited the application that issued as the ’975 Patent as prior art.

Case Timeline

Date	Event
2005-04-29	Priority Date for ’296, ’578, and ’048 Patents
2005-12-09	Priority Date for ’136 Patent
2008-01-25	Priority Date for ’975 Patent
2008-12-23	Priority Date for ’436 Patent
2010-07-13	U.S. Patent No. 7,757,048 Issues
2010-09-28	U.S. Patent No. 7,805,578 Issues
2011-04-12	U.S. Patent No. 7,924,296 Issues
2011-06-21	U.S. Patent No. 7,966,436 Issues
2012-04-03	U.S. Patent No. 8,151,136 Issues
2012-09-25	U.S. Patent No. 8,275,975 Issues
2014-06-20	Alleged Notice of ’975 Patent via USPTO Office Action
2024-12-03	Plaintiff sends notice letter to Defendant
2025-03-13	Plaintiff sends follow-up notice letter to Defendant
2025-04-15	Defendant responds to Plaintiff's notice letter
2025-09-25	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,924,296 - System and method for DMA controlled image processing

The Invention Explained

• Problem Addressed: The patent’s background describes conventional image processing systems that rely on a "frame buffer," a large and power-intensive memory, to store intermediate images during complex operations like blending images of different resolutions or color spaces. This increases system cost, complexity, and power consumption (’296 Patent, col. 1:41-59).
• The Patented Solution: The invention proposes a system that processes multiple image streams "on the fly" without a dedicated display storage frame buffer. It utilizes a Direct Memory Access (DMA) fetching module that fetches small portions ("tiles") of source images, sends them through processing logic (e.g., for scaling, color space conversion, and alpha blending), and generates a combined output for display, thereby minimizing the need for large intermediate memory buffers (’296 Patent, col. 2:4-14, Fig. 1).
• Technical Importance: This approach reduces memory bandwidth and power consumption, which is particularly valuable in resource-constrained environments like mobile devices (’296 Patent, col. 2:57-62).

Key Claims at a Glance

• The complaint asserts exemplary independent claim 21 (Compl. ¶10).
• Essential elements of claim 21 (a method) include:
  • transferring each of a plurality of images to one of a plurality of DMA channels;
  • fetching a plurality of image tiles of pixel data in a certain fetching order from the images;
  • blending the fetched image tiles to generate a combined image;
  • wherein the plurality of images are of different resolution, orientation, and/or color space.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,805,578 - Data processor apparatus and memory interface

The Invention Explained

• Problem Addressed: The patent’s background explains that in parallel processing architectures like SIMD (Single Instruction, Multiple Data), distributing the same data to multiple processing units often requires a dedicated "broadcast bus." This bus consumes significant physical chip area, leading to "routing congestion" and potential performance issues (’578 Patent, col. 1:45-col. 2:18).
• The Patented Solution: The invention proposes eliminating the dedicated broadcast bus by reusing the existing memory bus infrastructure. An array controller transmits "broadcast data" to a memory interface, which in turn writes copies of that data to the local memories associated with each processing unit. The processing units then access the broadcast data from their local memory, obviating the need for a separate, area-intensive bus (’578 Patent, Abstract; col. 8:51-62; Fig. 2).
• Technical Importance: This design reduces chip area and complexity, which are critical constraints in integrated circuit manufacturing, while potentially increasing performance compared to bit-serial broadcast methods (’578 Patent, col. 2:19-23).

Key Claims at a Glance

• The complaint asserts exemplary independent claim 1 (Compl. ¶21).
• Essential elements of claim 1 (an apparatus) include:
  • a plurality of memories;
  • a plurality of processing units respectively coupled to the memories;
  • an interface coupled to the memories by at least one data bus, configured to control access using an "identifier" to identify memory locations;
  • an array controller configured to provide "broadcast data" to the memory locations via the interface and data bus.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,757,048 - Data processor apparatus and memory interface

• Technology Synopsis: Belonging to the same family as the ’578 Patent, this patent addresses the problem of routing congestion from dedicated broadcast buses in parallel processors (’048 Patent, col. 2:19-23). The solution involves using a controller to transmit data intended for multiple processor units to memory, from which the units then retrieve it, thereby reusing the memory bus for broadcast operations (’048 Patent, col. 2:27-36).
• Asserted Claims: Exemplary independent claim 1 is asserted (Compl. ¶32).
• Accused Features: The complaint accuses Nvidia products based on "Tensor Core" GPU architectures (Hopper, Blackwell) and combined CPU-GPU architectures (Grace Hopper, Grace Blackwell) (Compl. ¶31).

U.S. Patent No. 8,275,975 - Sequencer controlled system and method for controlling timing of operations of functional units

• Technology Synopsis: The patent describes how a main processor in a complex System-on-Chip (SoC) can become a bottleneck by having to constantly monitor the status of various distributed functional units (’975 Patent, col. 1:40-42). The invention is a hardware "sequencer" that offloads this task, managing the timing and execution of operations across these units based on stored instructions, triggers, and responses, thereby freeing the main processor and enabling greater parallelism (’975 Patent, Abstract).
• Asserted Claims: Exemplary independent claim 1 is asserted (Compl. ¶43).
• Accused Features: The complaint accuses Nvidia products supporting "Multi-Instance GPU" (MIG) technology (Compl. ¶42).

U.S. Patent No. 7,966,436 - Data transmitter having high and low speed transmission units

• Technology Synopsis: This patent addresses the need for an efficient interface between a data processor and a display device that handles different types of data (’436 Patent, col. 1:39-44). The invention is a data transmitter with two modes: a high-speed, unidirectional mode for transmitting large "primary data" (e.g., image data) and a low-speed, bi-directional mode for smaller "secondary data" (e.g., control commands), optimizing power and bandwidth (’436 Patent, Abstract; col. 2:1-3).
• Asserted Claims: Exemplary independent claim 1 is asserted (Compl. ¶55).
• Accused Features: The complaint accuses Nvidia products incorporating a Display Serial Interface (DSI) (Compl. ¶54).

U.S. Patent No. 8,151,136 - Method and device for correcting code data error

• Technology Synopsis: The patent addresses the problem of system boot failures caused by errors in boot code stored in nonvolatile memory (’136 Patent, col. 3:42-50). The solution is a method for ensuring boot reliability by using a primary and a backup copy of the boot code. If an error is detected in the primary code, the system attempts to correct it (if a 1-bit error) or loads the code from the backup area (if a larger error), thus providing resilience against data corruption (’136 Patent, Abstract; Fig. 6).
• Asserted Claims: Exemplary independent claim 1 is asserted (Compl. ¶66).
• Accused Features: The complaint accuses Nvidia's Jetson AGX Orin Series System-on-Module, which allegedly includes a redundant bootloader system with an "A/B Slot Layout" (Compl. ¶65, ¶68).

III. The Accused Instrumentality

Product Identification

• The complaint targets a broad range of Defendant's semiconductor products, including GPUs, SoCs, and mobile processors. These are grouped into several categories across the infringement counts:
  • GPUs with Multi-Plane Overlay functionality, such as those with Pascal, Turing, Ampere, and Ada architectures (e.g., GTX10 through RTX40 series) (Compl. ¶9).
  • Products using "Tensor Core" GPU architectures like Hopper and Blackwell (e.g., H100, B200) and combined CPU-GPU "Superchip" architectures like Grace Hopper and Grace Blackwell (Compl. ¶20, ¶31).
  • Products supporting "Multi-Instance GPU" (MIG) technology, such as the A100 and H100 series GPUs (Compl. ¶42).
  • Products with a Display Serial Interface (DSI), including Tegra X1, Jetson TX1/TX2, and Jetson Nano products (Compl. ¶54).
  • The Jetson AGX Orin Series System-on-Module containing an NVIDIA Orin Series SoC (Compl. ¶65).

Functionality and Market Context

• The accused products represent core components of Defendant’s business in high-performance computing, artificial intelligence, professional visualization, and embedded/automotive applications. The complaint alleges that specific advertised technical features map to the patented inventions, including "blending among multiple display windows," the "Tensor Memory Accelerator (TMA)," "GigaThread thread Scheduler," "Multi-Instance GPU (MIG)," and a bootloader with "backup copies" in an "A/B Slot Layout" (Compl. ¶12, ¶23, ¶46, ¶68).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

’296 Patent Infringement Allegations

Since the complaint references a claim-chart exhibit that is not provided, the narrative infringement theory is summarized here. The complaint alleges that Defendant’s GPUs featuring "Multi-Plane Overlay" functionality infringe claim 21 of the ’296 Patent (Compl. ¶9). The theory appears to be that this functionality performs the claimed method of processing images from different sources without a full frame buffer. The complaint cites Defendant’s technical manuals that describe "[l]ayered blending among all windows," suggesting Plaintiff's position is that the accused products fetch data from multiple image planes (the "plurality of images"), blend them on the fly (the "blending" step), and output a combined image, thereby meeting the claim limitations (Compl. ¶12).

• Identified Points of Contention:
  • Technical Questions: A factual dispute may arise over whether the "Multi-Plane Overlay" feature operates on images that are of "different resolution, orientation, and/or color space" as required by the claim. Evidence will be needed to show that the accused blending function is not limited to images with uniform properties.
  • Scope Questions: The analysis may question whether the data units fetched by the accused products qualify as "image tiles of pixel data" within the meaning of the claim.

’578 Patent Infringement Allegations

Since the complaint references a claim-chart exhibit that is not provided, the narrative infringement theory is summarized here. The complaint alleges that Defendant’s Tensor Core GPU architectures infringe claim 1 of the ’578 Patent by implementing the claimed memory interface apparatus (Compl. ¶20). The infringement theory appears to center on features like the "Tensor Memory Accelerator (TMA)" and "GigaThread thread Scheduler" (Compl. ¶23). Plaintiff’s theory may be that these components collectively function as the claimed "interface" and "array controller" that manage the distribution of data to multiple processing cores by writing to and coordinating reads from shared memory, thus performing the function of a broadcast bus without being a dedicated physical bus structure (Compl. ¶23-24).

• Identified Points of Contention:
  • Technical Questions: A key question will be whether the operational mechanism of the TMA and thread scheduler is technically equivalent to the claimed apparatus. The patent depicts a distinct controller, memory interface, and processor units (’578 Patent, Fig. 2), and the court will need to determine if Defendant's more integrated architecture functions in the same way to achieve the same result.
  • Scope Questions: A central dispute may be whether the data managed by the TMA constitutes "broadcast data" as understood in the patent. This raises the question of whether the term refers generally to any data sent to multiple units or specifically to the simultaneous transmission of identical data packets in a SIMD context.

V. Key Claim Terms for Construction

For the ’296 Patent

• The Term: "blending the fetched plurality of image tiles" (from claim 21).
• Context and Importance: This term is central to the claimed method. Its scope will determine whether the "layered blending" allegedly performed by Defendant’s Multi-Plane Overlay feature constitutes infringement. Practitioners may focus on this term because the complaint explicitly links it to Defendant's advertised "blending" functionality (Compl. ¶12).
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The detailed description discusses the processing steps broadly, and while it mentions "alpha blending," the claim language itself is not so limited, potentially covering any method of combining pixel data from multiple tiles to form a composite image (’296 Patent, col. 6:22-29).
  • Evidence for a Narrower Interpretation: The abstract and summary of the invention repeatedly frame the invention in the context of "alpha blending" (’296 Patent, Abstract; col. 2:2-5). This could support an argument that "blending" is limited to mathematical alpha composition and does not cover simple layering or overlaying of opaque pixels.

For the ’578 Patent

• The Term: "broadcast data" (from claim 1).
• Context and Importance: The patented apparatus is designed to handle the distribution of "broadcast data" without a dedicated bus. Whether the data managed by Defendant’s TMA and scheduler qualifies as "broadcast data" will be a critical issue for infringement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification of the related ’048 Patent defines the concept as "data intended for each processor unit" (’048 Patent, col. 2:40-41). This suggests a functional definition based on intent, which could encompass a wide variety of data distribution schemes in a parallel architecture.
  • Evidence for a Narrower Interpretation: The patent’s background section is rooted in the context of SIMD (Single Instruction, Multiple Data) architectures, where "broadcast bus" is a term of art for distributing identical instructions or data to all processing elements (’578 Patent, col. 1:45-58). This context may support a narrower definition tied to the simultaneous distribution of identical data, as opposed to merely coordinated data access.

VI. Other Allegations

• Indirect Infringement: For all asserted patents, the complaint alleges induced infringement, citing Defendant’s publication of technical manuals, programming guides (e.g., CUDA), and developer blogs that allegedly instruct customers and end-users to configure and use the accused products in an infringing manner (Compl. ¶12, ¶23, ¶46, ¶57, ¶68). Contributory infringement is also alleged on the basis that the accused software and hardware functionalities (e.g., MIG, TMA, DSI) are material components especially made for infringement and are not staple articles of commerce (Compl. ¶13, ¶24, ¶47, ¶58, ¶69).
• Willful Infringement: The complaint alleges willful infringement based on both pre-suit and post-suit knowledge. For five of the six patents, pre-suit knowledge is alleged based on notice letters sent beginning on December 3, 2024 (Compl. ¶16, ¶27). For the ’975 patent, the complaint alleges a much earlier knowledge date of June 20, 2014, based on a USPTO Office Action in Defendant’s own patent prosecution that cited the ’975 patent’s application as prior art (Compl. ¶44, ¶50). Post-suit willfulness is alleged based on the filing of the complaint itself (Compl. ¶16, ¶27, ¶38, ¶50, ¶61, ¶72).

VII. Analyst’s Conclusion: Key Questions for the Case

• A central issue will be one of technical equivalence and aging: do the specific, and in some cases relatively simple, hardware architectures claimed in patents from the mid-to-late 2000s read on the functionality of today’s highly complex and integrated GPU and SoC architectures? For example, does the combination of Nvidia's Tensor Memory Accelerator and GigaThread scheduler function as the distinct "memory interface" and "array controller" claimed in the ’578 patent, or is there a fundamental architectural mismatch?
• The case will present a critical legal question on willful infringement: can pre-suit knowledge be established by a prior art rejection issued by the USPTO during the prosecution of a defendant’s unrelated patent application? The allegation regarding the ’975 patent will likely lead to significant dispute over what level of corporate awareness is required to establish knowledge for willfulness purposes.
• A key battleground will be one of definitional scope: can terms rooted in the technical context of their time be construed to cover modern implementations? For instance, can the "sequencer" of the ’975 patent, described as a tool for offloading a main processor, be interpreted to encompass Nvidia's "Multi-Instance GPU" technology, which partitions a GPU into virtual instances for workload parallelization? The outcome of such claim construction disputes may be determinative for several of the asserted patents.