DCT
1:25-cv-01629
Longitude Licensing Ltd v. Qualcomm Inc
Key Events
Amended Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Longitude Licensing Ltd. and Marlin Semiconductor Limited (Ireland)
- Defendant: Qualcomm Inc. (Delaware)
- Plaintiff’s Counsel: Mintz Levin Cohn Ferris Glovsky and Popeo PC; Miller Fair Henry PLLC
- Case Identification: 1:25-cv-01629, W.D. Tex., 11/24/2025
- Venue Allegations: Venue is based on allegations that Qualcomm maintains regular and established places of business in the Western District of Texas and has committed acts of patent infringement within the district.
- Core Dispute: Plaintiffs allege that Defendant’s semiconductor devices, including its Snapdragon series processors, infringe four patents related to fundamental semiconductor circuit designs.
- Technical Context: The technologies at issue involve circuit-level designs for filler cells, phase-locked loops, signal generation, and charge pumps, which are critical for the reliability, timing accuracy, and power management of complex integrated circuits.
- Key Procedural History: This First Amended Complaint follows an Original Complaint filed on October 8, 2025, a date Plaintiffs cite as establishing Defendant’s actual notice of the asserted patents for the purpose of alleging willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2009-02-04 | ’666 Patent Application Filing Date |
| 2010-04-27 | ’666 Patent Issue Date |
| 2011-07-20 | ’890 Patent Application Filing Date |
| 2011-08-15 | ’442 Patent Application Filing Date |
| 2013-02-05 | ’442 Patent Issue Date |
| 2013-06-11 | ’890 Patent Issue Date |
| 2017-09-29 | ’475 Patent Priority Date |
| 2017-11-01 | ’475 Patent Application Filing Date |
| 2018-10-16 | ’475 Patent Issue Date |
| 2025-10-08 | Original Complaint Filing Date |
| 2025-11-24 | First Amended Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,705,666 - Filler Circuit Cell, issued April 27, 2010
The Invention Explained
- Problem Addressed: In automated integrated circuit layout, "filler circuit cells" are used to fill physical gaps. The patent’s background describes a problem with prior art filler cells where connecting a transistor's gate directly to a power source makes it vulnerable to damage from voltage surges or "glitches," which can lead to the breakdown of the transistor’s dielectric layer (’666 Patent, col. 1:47-54).
- The Patented Solution: The invention introduces a "voltage stabilizing unit" positioned between the power source and the gate of the main transistor in the filler cell. This unit, composed of additional transistors, acts as a buffer to prevent voltage glitches from directly reaching and damaging the gate, thereby improving circuit reliability (’666 Patent, Abstract; col. 2:35-45; Fig. 2).
- Technical Importance: This design addresses a component-level reliability issue in high-density integrated circuits by protecting against electrical overstress without requiring complex external protection circuitry.
Key Claims at a Glance
- The complaint asserts independent claim 12 (Compl. ¶42-43).
- The essential elements of claim 12 are:
- A filler circuit cell, comprising:
- a decoupled capacitor comprising a first MOS transistor, wherein the source and drain of the first MOS transistor is connected to a first voltage source; and
- a voltage stabilizing unit disposed between the first voltage source, a gate of the first MOS transistor and a second voltage source to prevent damage for the gate of the first MOS transistor caused by sudden glitches,
- wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor.
U.S. Patent No. 8,461,890 - Phase and/or Frequency Detector, Phase-Locked Loop and Operation Method for the Phase-Locked Loop, issued June 11, 2013
The Invention Explained
- Problem Addressed: The patent’s background discusses the issue of "jittering" in phase-locked loops (PLLs), which can be caused by a "dead zone" in the phase/frequency detector (PFD). This dead zone occurs when the phase difference between input signals is too small for the PFD’s internal logic to operate correctly, leading to timing errors in the output signal (’890 Patent, col. 7:47-50).
- The Patented Solution: The invention adds a controllable delay circuit to the reset signal path of the PFD's flip-flops. This delay circuit dynamically alters a "prolonged period" of the reset pulse based on a "delay control signal" that is generated "according to the oscillating frequency" of the PLL's output. This ensures the reset pulse is always sufficiently long to operate correctly, thereby eliminating the dead zone and reducing jitter (’890 Patent, Abstract; col. 8:15-23).
- Technical Importance: The invention aims to improve the stability and precision of PLLs, which are fundamental building blocks for frequency synthesis, clock generation, and data recovery in modern electronics.
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶57-58).
- The essential elements of claim 1 are:
- a phase and/or frequency detector, comprising a first flip-flop and a second flip-flop;
- a logic gate configured for receiving signals from the flip-flops' data-output terminals;
- a control circuit configured for generating a delay control signal according to the oscillating frequency of the oscillating signal; and
- a delay circuit configured for altering a prolonged period according to the delay control signal to generate a reset signal for the flip-flops.
U.S. Patent No. 10,102,475 - Control Circuit for Generating Linear Term Signals, issued October 16, 2018
- Technology Synopsis: The patent addresses the challenge of performing linear multiplication, a key operation in artificial neural networks, using transistor circuits that inherently have non-linear characteristics (’475 Patent, col. 1:34-47). The invention discloses a specific control circuit using switches, capacitors, and an inverter to generate output currents proportional to the product of a data signal and a weighting signal, thereby achieving a linear calculation (’475 Patent, Abstract).
- Asserted Claims: Independent claim 1 (Compl. ¶75-76).
- Accused Features: A control circuit within the clock buffer and selector circuitry of the Qualcomm SDR865, as depicted in an annotated circuit diagram (Compl. ¶77, Fig. 3.6.5).
U.S. Patent No. 8,368,442 - Charge Pump, issued February 5, 2013
- Technology Synopsis: The patent describes a charge pump circuit, typically used within a PLL, designed to mitigate output jitter. The problem arises when the charge pump's output node becomes "floating" when its main switching transistors are off, making it susceptible to noise (’442 Patent, col. 2:50-54). The patented solution is a voltage regulator that dynamically adjusts the gate voltage of the switching transistors to stabilize the output current and provides a bias voltage to the output node when the main transistors are inactive, preventing the floating state (’442 Patent, Abstract).
- Asserted Claims: Independent claim 1 (Compl. ¶89-90).
- Accused Features: A charge pump located within the transmit path of the Qualcomm SDR865 device (Compl. ¶91).
III. The Accused Instrumentality
Product Identification
The complaint accuses the Qualcomm SDR865 integrated circuit and product families including the Snapdragon 8 Series, 800 Series, X Elite Series, and X Plus Series (Compl. ¶41, ¶56). These are alleged to be incorporated into consumer devices such as the Samsung Galaxy S20 series and Lenovo Yoga Slim 7X laptop (Compl. ¶22).
Functionality and Market Context
The accused products are System-on-a-Chip (SoC) processors that provide core functionality for high-end mobile devices (Compl. ¶22, ¶51). The infringement allegations do not target the SoCs as a whole, but rather specific, low-level circuits within them. The complaint uses third-party circuit analysis reports to identify: a filler cell within a voltage regulator start-up circuit (Compl. ¶44); a frequency phase detector (Compl. ¶59); a control circuit in a clock buffer (Compl. ¶77); and a charge pump in the transmit path (Compl. ¶91).
IV. Analysis of Infringement Allegations
’666 Patent Infringement Allegations
| Claim Element (from Independent Claim 12) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a decoupled capacitor comprising a first MOS transistor, wherein the source and drain of the first MOS transistor is connected to a first voltage source | A P-type MOS transistor within the SDR865's start-up circuit, with its source and drain connected to a voltage source labeled "VP." | ¶45 | col. 2:35-40 |
| a voltage stabilizing unit disposed between the first voltage source, a gate of the first MOS transistor and a second voltage source to prevent damage ... caused by sudden glitches | Circuitry shown in a pink box is identified as the stabilizing unit, disposed between voltage source VP, the gate of the first MOS transistor, and a second voltage source VSS. | ¶46 | col. 2:40-45 |
| wherein the voltage stabilizing unit comprises a second MOS transistor and a third MOS transistor | Specific transistors within the identified voltage stabilizing unit are labeled as the second and third MOS transistors. | ¶47 | col. 2:13-15 |
The complaint provides a circuit diagram from a "CircuitVision Analysis" of the Qualcomm SDR865, with colored boxes and annotations mapping components of a start-up circuit to the claimed "filler circuit cell" elements (Compl. ¶44-47, Fig. 13.14.4).
’890 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a phase and/or frequency detector, comprising a first flip-flop ... and a second flip-flop | Two DFF2 flip-flop circuits are identified within the SDR865 frequency phase detector. | ¶60-61 | col. 5:40-49 |
| a logic gate configured for receiving signals outputted from the first data-output terminal and the second data-output terminal | A "Test Multiplexer 1" circuit is alleged to be the logic gate receiving outputs from the two identified flip-flops. | ¶63 | col. 7:51-54 |
| a control circuit configured for generating a delay control signal according to the oscillating frequency of the oscillating signal | Signals labeled X_TPLL_PHDDCT and X_TPLL_PHD2DCT are identified as the delay control signals. | ¶64 | col. 8:15-18 |
| a delay circuit configured for altering a prolonged period according to the delay control signal to generate a reset signal to be outputted to the first reset terminal and the second reset terminal | Two circuits labeled "Delay 3" are identified as the delay circuit that receives the delay control signals and outputs a reset signal to the flip-flops. | ¶65 | col. 8:19-23 |
The complaint provides a circuit diagram of an accused frequency phase detector, using colored boxes to identify alleged flip-flops and a logic gate (Compl. ¶59-63, Fig. 3.1). A separate diagram is referenced to show that the frequency-divided signal originates from frequency divider circuits (Compl. ¶62, Fig. 3.7).
Identified Points of Contention
- Scope Questions: For the ’666 Patent, a central question may be whether the accused circuit, identified as part of a "start-up circuit for its voltage regulator" (Compl. ¶44), qualifies as a "filler circuit cell" as recited in the claim. The defense may argue that the accused component has a primary, active electrical function distinct from the structural gap-filling role often associated with filler cells.
- Technical Questions: For the ’890 Patent, a key issue may be whether the complaint provides sufficient evidence that the alleged "control circuit" generates the "delay control signal" according to the oscillating frequency as the claim requires. The analysis will likely focus on whether the accused "Delay 3" circuits are dynamically controlled based on feedback from the PLL's oscillating frequency or if they are controlled by other, unrelated system parameters.
V. Key Claim Terms for Construction
’666 Patent, Claim 12
- The Term: "filler circuit cell"
- Context and Importance: This term's definition is fundamental to the infringement case. Plaintiffs' theory maps elements of an active start-up circuit to this term (Compl. ¶44). If the term is construed narrowly to include only passive structures used for layout completion, the infringement argument may be weakened.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not provide a restrictive definition in the specification. The background describes filler cells as being "utilized... to fill the gaps within a cell unit" (’666 Patent, col. 1:22-23), a description that could arguably encompass any circuit placed in such a gap, regardless of its electrical function.
- Evidence for a Narrower Interpretation: The background section frames the context as "digital integrated circuit design" using "standard cell libraries" for "high automation in a layout design" (’666 Patent, col. 1:9-12). This context may support an interpretation limiting the term to components whose primary purpose is to satisfy layout and design rule constraints, rather than performing an active circuit function.
’890 Patent, Claim 1
- The Term: "a control circuit configured for generating a delay control signal according to the oscillating frequency of the oscillating signal"
- Context and Importance: This limitation describes the core inventive concept of adaptive delay control. Proving infringement requires showing that the accused device's delay is controlled via a feedback mechanism tied to the oscillating frequency. Practitioners may focus on this term because the complaint identifies the control signals but provides less detail on the mechanism that generates them (Compl. ¶64).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification discloses multiple embodiments for the control circuit, including one based on a frequency detector and another based on a voltage detector that monitors the VCO's control voltage (’890 Patent, Figs. 12-13). This suggests that "according to" does not require a direct frequency measurement and could be interpreted more broadly to cover indirect correlations.
- Evidence for a Narrower Interpretation: The embodiments described involve actively detecting either the frequency itself or a voltage directly proportional to it (’890 Patent, col. 9:48-10:24). This could support a narrower construction requiring a direct feedback loop, potentially excluding systems where delay values are set by static parameters or system states only loosely correlated with the instantaneous oscillating frequency.
VI. Other Allegations
Indirect Infringement
The complaint alleges both induced infringement and contributory infringement. Inducement is based on allegations that Qualcomm provides the accused chips to downstream manufacturers with the knowledge and intent that they be incorporated into infringing end-user products (Compl. ¶33, ¶49). Contributory infringement is based on allegations that the chips are a material part of the inventions, are not staple articles of commerce, and have no substantial non-infringing uses (Compl. ¶34, ¶50).
Willful Infringement
Willfulness is alleged based on Qualcomm’s continued infringement after receiving actual notice of the Asserted Patents, with notice alleged to have occurred no later than the filing date of the original complaint on October 8, 2025 (Compl. ¶32, ¶39).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "filler circuit cell" (’666 Patent), rooted in the context of semiconductor layout completion, be construed to read on an active component within a "start-up circuit for its voltage regulator output stage" as alleged in the complaint?
- A key evidentiary question will be one of functional operation: does the accused phase detector's control system generate its delay control signals "according to the oscillating frequency" as required by the ’890 Patent, or is there a fundamental mismatch in the technical control mechanism that governs the timing of its reset signals?
- The case will also turn on an evidentiary foundation: to what extent can Plaintiffs prove, beyond the annotated schematics provided, that the accused circuits operate in the specific manner required by the functional limitations in the asserted claims of the ’475 patent (linear signal generation) and ’442 patent (dynamic voltage regulation)?