DCT

1:25-cv-01647

Network System Tech LLC v. SK Hynix Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01647, W.D. Tex., 10/14/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant SK hynix America Inc. maintains a regular and established place of business in Austin, where personnel engage in activities related to the accused products, including supporting major customers within the district. Venue over SK hynix Inc. is asserted on the basis of it being a foreign entity.
  • Core Dispute: Plaintiff alleges that Defendant’s System-on-a-Chip (SoC) products, enterprise Solid-State Drives (SSDs), and controllers containing Network-on-Chip (NoC) technology infringe seven U.S. patents.
  • Technical Context: The lawsuit concerns Network-on-Chip (NoC) technology, a fundamental architecture for managing communication between numerous processing cores, memory blocks, and other functional units on a single, complex integrated circuit, which is critical to the performance and efficiency of modern electronics.
  • Key Procedural History: The complaint alleges that Defendants had pre-suit knowledge of at least some of the asserted patents as early as December 19, 2022. This allegation is based on Plaintiff's prior litigation against other semiconductor companies, including Arteris, Inc., a company from which Defendants allegedly license the accused interconnect technology. The complaint also alleges knowledge through Defendants' membership in RPX Corporation, a patent risk management firm. These allegations form the basis for the claim of willful infringement.

Case Timeline

Date Event
2002-10-08 Earliest Priority Date ('818, '449, '9893 Patents)
2004-03-17 Earliest Priority Date ('052 Patent)
2004-03-26 Earliest Priority Date ('849 Patent)
2004-05-18 Earliest Priority Date ('800 Patent)
2005-04-21 Earliest Priority Date ('2893 Patent)
2008-04-29 U.S. Patent No. 7,366,818 Issues
2008-05-13 U.S. Patent No. 7,373,449 Issues
2009-09-22 U.S. Patent No. 7,594,052 Issues
2009-11-03 U.S. Patent No. 7,613,849 Issues
2010-08-03 U.S. Patent No. 7,769,893 Issues
2011-12-06 U.S. Patent No. 8,072,893 Issues
2011-12-27 U.S. Patent No. 8,086,800 Issues
2022-12-19 Plaintiff initiates litigation against Arteris, Qualcomm, TI, and Samsung
2025-10-14 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,366,818 - *"INTEGRATED CIRCUIT COMPRISING A PLURALITY OF PROCESSING MODULES AND A NETWORK AND METHOD FOR EXCHANGING DATA USING SAME"*

The Invention Explained

  • Problem Addressed: The patent describes the problem of communication bottlenecks in complex integrated circuits where multiple processing modules communicate via a shared bus, which creates high loads and limits performance as only one device can transmit data at a time ('818 Patent, col. 1:25-35).
  • The Patented Solution: The invention proposes a Network-on-Chip (NoC) architecture that includes an "interface means" containing a "dropping means" for selectively discarding data packets exchanged between modules ('818 Patent, Abstract). This allows the interface, rather than the network itself, to control transaction completion and provides an alternative to more complex and resource-intensive end-to-end flow control mechanisms that guarantee delivery ('818 Patent, col. 6:29-43).
  • Technical Importance: This approach provided a method for managing on-chip data traffic that could offer a balance between the guaranteed delivery of expensive flow-control systems and the potential data loss of uncontrolled systems, aiming to improve efficiency without incurring maximum cost ('818 Patent, col. 5:7-13).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶154).
  • The essential elements of Claim 1 include:
    • An integrated circuit with multiple processing modules on the same chip.
    • A network-on-chip connecting a first module and a second module.
    • The connection supports transactions with outgoing and return messages.
    • At least one "interface means" for managing the interface between a module and the network.
    • The interface means comprises a "first dropping means for dropping data."
    • The dropping of data, and therefore transaction completion, can be controlled by the interface means.
  • The complaint does not explicitly reserve the right to assert dependent claims for the ’818 Patent.

U.S. Patent No. 7,373,449 - *"APPARATUS AND METHOD FOR COMMUNICATING IN AN INTEGRATED CIRCUIT"*

The Invention Explained

  • Problem Addressed: The patent addresses the inefficient utilization of resources in a Network-on-Chip, where a connection between modules may be "over dimensioned" for its actual requirements, leading to wasted network resources that could be used for other communications ('449 Patent, col. 7:21-26).
  • The Patented Solution: The invention describes a method where a module requests a connection by specifying its "desired connection properties" (e.g., throughput, latency) to a "communication manager." This manager forwards the request to a "resource manager," which determines if the network has sufficient resources to establish such a connection. This allows for the creation of independently configurable communication channels tailored to specific needs ('449 Patent, Abstract; col. 8:36-54).
  • Technical Importance: This method enables more dynamic and efficient allocation of on-chip network resources, allowing a single physical network to support diverse communication requirements simultaneously ('449 Patent, col. 7:27-33).

Key Claims at a Glance

  • The complaint asserts independent claim 10 (Compl. ¶165). The complaint notes that claims 1 and 3-5 have been statutorily disclaimed (Compl. ¶42, n.21).
  • The essential steps of method Claim 10 include:
    • A first module issuing a request for a connection to a second module to a "communication manager," where the request specifies desired "connection properties."
    • The communication manager forwarding the request to a "resource manager."
    • The resource manager determining if a target connection with the desired properties is available.
    • The resource manager responding with the availability to the communication manager.
    • Establishing the target connection based on the available properties.
  • The complaint does not explicitly reserve the right to assert dependent claims for the ’449 Patent.

U.S. Patent No. 7,594,052 - *"INTEGRATED CIRCUIT AND METHOD OF COMMUNICATION SERVICE MAPPING"*

  • Technology Synopsis: This patent addresses how to integrate processing modules that use different communication protocols onto a single NoC. It discloses a method of "communication service mapping," where a request from a module is mapped to a specific network connection based on a "communication service identification" (like a communication thread or address range), allowing different types of services to be managed over the same physical network (Compl. ¶¶58, 61).
  • Asserted Claims: Independent Claim 6 (Compl. ¶176).
  • Accused Features: The complaint alleges that Defendants' SoCs and related products implement a method of mapping communication services based on specific properties to connections according to a service identification, infringing the ’052 Patent (Compl. ¶¶58-61, 137).

U.S. Patent No. 7,613,849 - *"INTEGRATED CIRCUIT AND METHOD FOR TRANSACTION ABORTION"*

  • Technology Synopsis: The patent describes a system and method for aborting a transaction that has already been issued on a NoC. It discloses a "transaction abortion unit" that receives an abort request, initiates a discard of the transaction (e.g., in a request buffer), and issues a response indicating the success or failure of the abortion attempt (Compl. ¶¶73, 76). This provides a structured way to cancel in-flight operations.
  • Asserted Claims: Independent Claim 1 (Compl. ¶188).
  • Accused Features: The complaint alleges that the accused products contain an interconnect device with a transaction abortion unit located in a network interface for aborting transactions, thereby infringing the ’849 Patent (Compl. ¶¶73-76, 137).

U.S. Patent No. 7,769,893 - *"INTEGRATED CIRCUIT AND METHOD FOR ESTABLISHING TRANSACTIONS"*

  • Technology Synopsis: This patent discloses a method for address mapping within a NoC using an "address translation unit." This unit takes location information for a target module and a location within that module, arranges it as a single address, and uses that single address to determine both which module to route the message to and the specific location within it (Compl. ¶¶88, 91). This simplifies addressing from the perspective of the initiating module.
  • Asserted Claims: Independent Claim 4 (Compl. ¶200).
  • Accused Features: The accused products are alleged to use an address translation unit within a network interface for address mapping in a manner that infringes the ’9893 Patent (Compl. ¶¶88-91, 137).

U.S. Patent No. 8,072,893 - *"INTEGRATED CIRCUIT WITH DATA COMMUNICATION NETWORK AND IC DESIGN METHOD"*

  • Technology Synopsis: The patent describes a design method for NoCs to manage data transfer delays. The method involves identifying a communication channel with a delay exceeding a threshold and then inserting a specific number of data storage elements (M*N, where N is the data package size) to introduce a compensating delay, thereby allowing the rest of the chip network to operate without being limited by the slowest path (Compl. ¶¶103, 106).
  • Asserted Claims: Independent Claim 10 (Compl. ¶212).
  • Accused Features: The complaint alleges that Defendants' accused products are made or designed by a process that involves identifying and mitigating data transfer delays in a NoC in a way that infringes the ’2893 Patent (Compl. ¶¶103-106, 137).

U.S. Patent No. 8,086,800 - *"INTEGRATED CIRCUIT AND METHOD FOR BUFFERING TO OPTIMIZE BURST LENGTH IN NETWORKS ON CHIPS"*

  • Technology Synopsis: This patent focuses on optimizing data transfer efficiency by buffering data to create optimal "burst lengths." It discloses interconnect modules with determination units that determine an "optimal amount" of data to buffer before transferring it over the network, based on communication properties. This allows data to be aggregated into larger, more efficient bursts (Compl. ¶¶118, 121).
  • Asserted Claims: Independent Claim 12 (Compl. ¶222).
  • Accused Features: The accused products are alleged to employ data buffering with determination units to optimize burst lengths for data transfer over a NoC, infringing the ’800 Patent (Compl. ¶¶118-121, 137).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies the accused instrumentalities as "SoCs containing network-on-chip technology" and "Products, modules, components, and/or systems (e.g., memory units, enterprise SSDs, controllers, etc.) containing network-on-chip technology" (Compl. ¶137). An exemplary product series cited is the PE8000 enterprise SSD series, which allegedly includes controllers developed by Defendants (Compl. ¶135). The complaint displays this information in a table, defining the general categories of accused products (Compl. ¶137, p. 47).

Functionality and Market Context

  • The complaint alleges that these products incorporate an on-chip network interconnect to manage communications between multiple processors, memory units, and other functional components residing on a single chip (Compl. ¶¶132, 134). This interconnect technology is alleged to be licensed from Arteris, Inc. or be a derivative thereof (Compl. ¶135). The accused products are positioned in the market as memory units and enterprise SSDs from a leading semiconductor company (Compl. ¶135).

IV. Analysis of Infringement Allegations

The complaint references, but does not include, claim chart exhibits for the asserted patents (Compl. ¶140). The following summary is based on the narrative infringement allegations in the complaint body.

’818 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an integrated circuit comprising a plurality of processing modules (M, S) said modules being disposed on the same chip, and a network (N; RN) arranged for providing at least one connection... The accused SoCs are integrated circuits containing multiple processing modules (e.g., processors, memory) connected by a network-on-chip. ¶¶30, 132, 137 col. 1:17-25
wherein said modules communicate via a network on chip... The accused products' internal modules communicate using the incorporated NoC technology. ¶¶134, 137 col. 6:49-56
at least one interface means (ANIP, PNIP) for managing the interface between a module... and the network... The accused products contain network interfaces that manage communication between the processing modules and the on-chip network fabric. ¶¶28, 137 col. 6:36-40
wherein said interface means (ANIP, PNIP) comprises a first dropping means (DM) for dropping data... The network interfaces in the accused products allegedly include a mechanism for dropping data as part of their traffic and quality-of-service management. ¶¶28, 31 col. 6:39-41
wherein the dropping of data and therefore the transaction completion can be controlled by the interface means. By providing the capability to drop data at the interface level, the accused products' interfaces allegedly control whether and how transactions are completed. ¶¶28, 31 col. 6:41-43
  • Identified Points of Contention:
    • Scope Questions: A central question may be the interpretation of "dropping means." The analysis may focus on whether this term requires a specific, dedicated hardware block for dropping data as depicted in the patent's figures (e.g., '818 Patent, Fig. 2), or if it can read on more general quality-of-service (QoS) logic within the accused Arteris interconnect fabric that may result in dropped packets.
    • Technical Questions: The case may require evidence demonstrating that in the accused products, it is the "interface means" that "controls" transaction completion by dropping data, as opposed to other network management or protocol-level mechanisms.
      ’449 Patent Infringement Allegations
Claim Element (from Method Claim 10) Alleged Infringing Functionality Complaint Citation Patent Citation
the first module issuing a request for a connection with the second module to a communication manager, wherein the request comprises desired connection properties... The accused products allegedly feature a process where an initiator module requests a connection with specific properties (e.g., bandwidth, latency) to establish communication over the NoC. ¶¶43, 46, 137 col. 10:8-15
the communication manager forwarding the request to a resource manager; The accused products' interconnect system allegedly includes a logical step where the initial connection request is passed to a resource management function. ¶¶43, 46 col. 10:16-17
the resource manager determining whether a target connection with the desired connection properties is available; This resource management function in the accused products allegedly checks the availability of network resources (e.g., link bandwidth, buffer space) to satisfy the requested connection properties. ¶¶43, 46 col. 10:18-20
the resource manager responding with the availability... and the target connection... being established based on the available properties... Based on the resource check, the accused system allegedly establishes a communication channel configured with the available properties that meet the request. ¶¶43, 46 col. 10:21-27
  • Identified Points of Contention:
    • Scope Questions: The dispute may turn on the definitions of "communication manager" and "resource manager." The question will be whether these terms require distinct, separate hardware or software entities, as suggested by some patent figures ('449 Patent, Fig. 3), or if they can describe different logical functions performed by a single, unified interconnect management unit in the accused products.
    • Technical Questions: Evidence will be needed to show that the accused products perform the specific, sequential steps as claimed. The defense may argue that their system establishes connections through a different, non-infringing process that does not map onto the claimed manager-to-manager interaction.

V. Key Claim Terms for Construction

  • For the ’818 Patent:

    • The Term: "dropping means"
    • Context and Importance: This term is the core of the asserted claim's inventive concept. Its construction will determine whether the quality-of-service and traffic management functionalities in the accused products, which may involve discarding packets under certain conditions, fall within the scope of the claim.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The claim language itself is functional ("means for dropping data"), which may support an interpretation covering any component or logic that performs the function of dropping data to control transaction completion (Compl. ¶28).
      • Evidence for a Narrower Interpretation: The specification explicitly shows a "dropping manager DM" as a distinct block within the network interface (ANIP, PNIP) ('818 Patent, Fig. 2). A defendant may argue that "dropping means" should be limited to a structure corresponding to this disclosed embodiment.

  • For the ’449 Patent:

    • The Term: "resource manager"
    • Context and Importance: The claim requires a "communication manager" to forward a request to a "resource manager." The definition of "resource manager" is critical to determining whether the accused products perform this required step. If the accused product uses a single, monolithic entity to handle all aspects of connection requests, it may not infringe.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent describes the resource manager's function as "managing the resources of the network N" ('449 Patent, col. 7:40-42). This functional description could support an interpretation covering any logical process that allocates network hardware, regardless of its specific implementation.
      • Evidence for a Narrower Interpretation: The specification depicts the "communication managing means CM" and "resource managing means RM" as separate blocks ('449 Patent, Fig. 3). A defendant may argue that the claim requires two structurally or functionally distinct entities and that a single, integrated management unit does not meet this limitation.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement based on Defendants actively encouraging customers, OEMs, and end-users to use the accused products in an infringing manner. This encouragement is allegedly provided through marketing materials, product briefs, data sheets, technical support, and a "Sales Kit" available on Defendants' website that provides information on product strengths and upcoming products (Compl. ¶¶141, 146, 150).
  • Willful Infringement: Willfulness is alleged based on Defendants' purported knowledge of the patents prior to the lawsuit. The complaint asserts this knowledge stems from at least two sources: (1) Plaintiff's December 2022 litigation against Arteris, whose technology Defendants allegedly license and use, and (2) Defendants' membership in RPX Corporation, which allegedly provides litigation alerts and patent analysis to its members (Compl. ¶¶24-25, 149, 162).

VII. Analyst’s Conclusion: Key Questions for the Case

This dispute appears to center on highly technical aspects of Network-on-Chip architecture and the extent to which commercial implementations map onto the specific structures and methods claimed in the asserted patents. The central questions for the court will likely be:

  1. A core issue will be one of structural and functional mapping: Do the accused products, which allegedly use Arteris NoC IP, contain discrete components or perform distinct logical steps that correspond to the claimed "dropping means" ('818 Patent) or the separate "communication manager" and "resource manager" entities ('449 Patent)? The case may hinge on whether these claim terms are interpreted broadly to cover integrated functions or narrowly to require separate, dedicated structures as depicted in the patents.
  2. A second key issue will be one of process infringement and design methodology: For patents like the '2893 patent that claim a method of designing an integrated circuit, what evidence can be presented to demonstrate that Defendants' internal design and verification processes for their SoCs practice the claimed steps of identifying delay thresholds and inserting specific data storage elements?
  3. A pivotal evidentiary question will concern willfulness and pre-suit knowledge: The complaint’s allegations of knowledge are tied to Defendants' relationship with a third-party technology vendor (Arteris) and a patent risk-management firm (RPX). A key factual dispute will likely be what specific information about the asserted patents, if any, was actually received and understood by Defendants through these channels prior to the filing of the lawsuit.