DCT

1:25-cv-01648

Network System Tech LLC v. Advanced Micro Devices Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01648, W.D. Tex., 10/14/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because both Defendants have committed acts of infringement and maintain a regular and established place of business in Austin, where personnel work on activities related to the accused System-on-a-Chip products.
  • Core Dispute: Plaintiff alleges that Defendants’ System-on-a-Chip (SoC) products, including the Versal family of adaptive SoCs and certain AMD GPUs, infringe nine patents related to Network-on-Chip (NoC) interconnect architectures and processor efficiency.
  • Technical Context: The technology at issue is Network-on-Chip (NoC), an approach to designing the communication subsystem between various processing cores, memory, and other intellectual property blocks on a single, complex semiconductor chip.
  • Key Procedural History: The complaint alleges Defendants had pre-suit knowledge of the asserted patents based on several events. These include Plaintiff’s December 2022 lawsuits against other semiconductor companies (including Arteris, an alleged technology partner of Defendants), reports on that litigation by patent risk management group RPX (of which AMD is an alleged member), and numerous instances where the asserted patents were cited during the patent prosecution of applications assigned to Xilinx and later AMD. The complaint also details AMD’s February 2022 acquisition of Xilinx, asserting that Xilinx's knowledge and liability are imputed to AMD.

Case Timeline

Date Event
2002-05-24 U.S. Patent No. 7,290,157 Priority Date
2002-10-08 U.S. Patent No. 7,366,818 Priority Date
2002-10-08 U.S. Patent No. 7,373,449 Priority Date
2002-10-08 U.S. Patent No. 7,769,893 Priority Date
2004-03-17 U.S. Patent No. 7,594,052 Priority Date
2004-03-26 U.S. Patent No. 7,613,849 Priority Date
2004-05-18 U.S. Patent No. 8,086,800 Priority Date
2004-11-24 U.S. Patent No. 7,779,205 Priority Date
2005-04-21 U.S. Patent No. 8,072,893 Priority Date
2007-10-30 U.S. Patent No. 7,290,157 Issued
2008-04-29 U.S. Patent No. 7,366,818 Issued
2008-05-13 U.S. Patent No. 7,373,449 Issued
2009-09-22 U.S. Patent No. 7,594,052 Issued
209-11-03 U.S. Patent No. 7,613,849 Issued
2010-08-03 U.S. Patent No. 7,769,893 Issued
2010-08-17 U.S. Patent No. 7,779,205 Issued
2011-12-06 U.S. Patent No. 8,072,893 Issued
2011-12-27 U.S. Patent No. 8,086,800 Issued
2022-02-14 AMD completes acquisition of Xilinx
2022-12-19 Plaintiff files lawsuits against Arteris, Qualcomm, TI, and Samsung
2025-10-14 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,366,818 - *Integrated Circuit Comprising a Plurality of Processing Modules and a Network and Method for Exchanging Data Using Same* (Issued Apr. 29, 2008)

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of guaranteeing transaction completion in complex Network-on-Chip (NoC) systems, noting that traditional methods like end-to-end flow control can be expensive to implement (’818 Patent, col. 5:8-13).
  • The Patented Solution: The invention proposes a system where the network interfaces, rather than the network routers themselves, are responsible for managing transaction completion. It introduces a "dropping means" located within the interface that can be controlled to selectively drop data packets, providing a more flexible and potentially lower-cost alternative to ensuring that transactions either complete or fail in a known state (’818 Patent, Abstract; col. 6:29-41).
  • Technical Importance: This approach provides a mechanism for implementing quality-of-service (QoS) and managing data flow in an NoC without relying on rigid, guaranteed-delivery schemes for all transactions, which can improve efficiency (Compl. ¶40).

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 1 (Compl. ¶223).
  • The essential elements of independent Claim 1 include:
    • An integrated circuit with a plurality of processing modules on the same chip.
    • A network on chip providing a connection between modules for transactions.
    • At least one "dropping means" for dropping data exchanged between the modules.
    • At least one "interface means" for managing the module-to-network interface.
    • The interface means comprises a "first dropping means."
    • The dropping of data and transaction completion can be "controlled by the interface means."

U.S. Patent No. 7,373,449 - *Apparatus and Method for Communicating in an Integrated Circuit* (Issued May 13, 2008)

The Invention Explained

  • Problem Addressed: In complex SoCs, statically allocating network resources often leads to inefficiency, as connections may be "over dimensioned" for worst-case scenarios, leaving bandwidth and other resources unused much of the time (’449 Patent, col. 7:25-30).
  • The Patented Solution: The patent describes a system for dynamic resource allocation. A "communication manager" receives connection requests from modules that specify desired "connection properties" (e.g., throughput, latency). This manager forwards the request to a "resource manager," which checks the availability of network resources and establishes a connection based on the available, rather than fixed, properties. This allows connection channels to be configured independently and more efficiently (’449 Patent, Abstract; col. 8:39-54).
  • Technical Importance: This method allows for more efficient utilization of on-chip network resources by tailoring connections to the specific requirements of a given communication task, rather than using a one-size-fits-all approach (Compl. ¶60).

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 10 (Compl. ¶234). The Plaintiff has statutorily disclaimed claims 1 and 3-5 (Compl. ¶56, fn. 47).
  • The essential steps of independent method Claim 10 include:
    • A first module issuing a request for a connection with "desired connection properties" to a "communication manager."
    • The communication manager forwarding the request to a "resource manager."
    • The resource manager determining if a target connection with the desired properties is available.
    • The resource manager responding with the availability.
    • Establishing the connection based on the available properties of the communication channels.

Multi-Patent Capsules

  • U.S. Patent No. 7,594,052 (Issued Sep. 22, 2009): Integrated Circuit and Method of Communication Service Mapping

    • Technology Synopsis: The patent describes a method for mapping a requested communication service to a specific network connection. A processing module requests a service based on specific properties and a "communication service identification" (such as a communication thread or an address range), and a network interface maps this request to a connection with a corresponding set of properties (Compl. ¶77, ¶80).
    • Asserted Claims: At least Claim 6 (Compl. ¶245).
    • Accused Features: The interconnect technology in the Accused Products, which allegedly maps communication requests to network connections with specific properties (Compl. ¶204-205, ¶245).

  • U.S. Patent No. 7,613,849 (Issued Nov. 3, 2009): Integrated Circuit and Method for Transaction Abortion

    • Technology Synopsis: The patent discloses a "transaction abortion unit," typically within a network interface, that can abort a transaction. This unit receives an abort request, initiates a discard of the transaction (e.g., from a request buffer), and issues a response indicating the success or failure of the abortion attempt (Compl. ¶93, ¶96).
    • Asserted Claims: At least Claim 1 (Compl. ¶257).
    • Accused Features: The interconnect technology in the Accused Products, which allegedly includes functionality to abort in-flight transactions between modules (Compl. ¶204-205, ¶257).

  • U.S. Patent No. 7,769,893 (Issued Aug. 3, 2010): Integrated Circuit and Method for Establishing Transactions

    • Technology Synopsis: This patent describes an "address translation unit" within a network interface for address mapping in an NoC. The unit arranges "first information" (e.g., a connection identifier) and "second information" (e.g., a memory address within a module) into a single address to determine which module is being addressed and the particular location within it (Compl. ¶109, ¶112).
    • Asserted Claims: At least Claim 4 (Compl. ¶269).
    • Accused Features: The addressing and routing mechanisms within the Accused Products' interconnect fabric (Compl. ¶204-205, ¶269).

  • U.S. Patent No. 8,072,893 (Issued Dec. 6, 2011): Integrated Circuit with Data Communication Network and IC Design Method

    • Technology Synopsis: The patent claims a method of designing an IC by identifying a communication channel with a data transfer delay exceeding a threshold. In response, the method involves inserting a specific number of "MN data storage elements" to introduce a delay of MN cycles, where N is the data package size, thereby managing timing across the network (Compl. ¶130, ¶133).
    • Asserted Claims: At least Claim 10 (Compl. ¶281).
    • Accused Features: The design methods and resulting structures of the Accused Products, which allegedly use inserted delay elements to manage data transfer delays in their NoC (Compl. ¶204-205, ¶281).

  • U.S. Patent No. 8,086,800 (Issued Dec. 27, 2011): Integrated Circuit and Method for Buffering to Optimize Burst Length in Networks on Chips

    • Technology Synopsis: The patent discloses a system for optimizing data burst length in an NoC. Interconnect modules buffer data at both the requesting (master) and responding (slave) modules. "Determination units" configure an optimal amount of data to buffer before initiating a transfer, based on the communication properties of the connection (Compl. ¶150, ¶153).
    • Asserted Claims: At least Claim 12 (Compl. ¶291).
    • Accused Features: The data buffering and burst transfer mechanisms within the Accused Products' interconnect fabric (Compl. ¶204-205, ¶291).

  • U.S. Patent No. 7,290,157 (Issued Oct. 30, 2007): Configurable Processor with Main Controller to Increase Activity of at Least One of a Plurality of Processing Units Having Local Program Counters

    • Technology Synopsis: This patent describes a processor architecture for power efficiency. A main control unit processes instructions from a main instruction memory that explicitly control the activity of a plurality of processing units, allowing individual units to be completely switched off and then switched back on by the main controller, rather than by their own local controllers (’157 Patent, Abstract; Compl. ¶166).
    • Asserted Claims: At least Claim 1 (Compl. ¶303).
    • Accused Features: The power management architecture of processors within the Accused Products, including AMD GPUs (Compl. ¶206, ¶303).

  • U.S. Patent No. 7,779,205 (Issued Aug. 17, 2010): Coherent Caching of Local Memory Data

    • Technology Synopsis: The patent describes a multi-processor system that enables coherent caching of a local memory. The local memory, associated with a first processor, is equipped with two ports: a first for direct access by its associated processor, and a second for access by other processors via the main system bus, allowing shared, coherent access to what would otherwise be private local memory (Compl. ¶186, ¶189).
    • Asserted Claims: At least Claim 7 (Compl. ¶314).
    • Accused Features: The memory and caching architecture within the Accused Products, including AMD GPUs (Compl. ¶206, ¶314).

III. The Accused Instrumentality

  • Product Identification: The complaint identifies the "Accused Products" as "Versal processors and SoCs containing network-on-chip technology," "AMD or Xilinx integrated circuits containing network-on-chip technology," and "AMD GPUs (e.g., Vega Series Processors)" (Compl. ¶206).
  • Functionality and Market Context: The Accused Products are complex System-on-a-Chip (SoC) devices that integrate multiple processors, memory units, and other functional blocks onto a single chip (Compl. ¶201). The complaint alleges that these products, particularly the Versal SoCs, utilize a Network-on-Chip (NoC) architecture for communication between these internal components (Compl. ¶202). Specifically, the complaint alleges the Versal SoCs incorporate interconnect technology from Arteris, a third-party IP provider (Compl. ¶204, fn. 55). These SoCs are foundational components in a wide range of modern electronics, including data centers, embedded systems, and consumer electronics (Compl. ¶201).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint incorporates by reference claim chart exhibits that were not included in the filing document (Compl. ¶209). The narrative infringement theories are summarized below.

  • U.S. Patent No. 7,366,818 Infringement Allegations
    The complaint alleges that the Accused Products, such as Versal SoCs, infringe at least Claim 1 of the ’818 Patent (Compl. ¶223). The theory appears to be that the products' network interfaces contain functionality equivalent to the claimed "dropping means" and "interface means," which are used to manage transaction completion by controlling the dropping of data (Compl. ¶37, ¶40). This functionality is allegedly part of the NoC interconnect fabric used in the devices (Compl. ¶204-205).
  • U.S. Patent No. 7,373,449 Infringement Allegations
    The complaint alleges that the Accused Products practice the method of at least Claim 10 of the ’449 Patent (Compl. ¶234). The infringement theory is that when establishing a communication link, the products' interconnect fabric performs the claimed steps of receiving a connection request with desired "connection properties," forwarding it to a "resource manager" that determines resource availability, and establishing the connection based on those available resources (Compl. ¶58). This functionality is also attributed to the alleged Arteris interconnect technology within the Accused Products (Compl. ¶204-205).
  • Identified Points of Contention:
    • Scope Questions: For the ’818 Patent, a potential point of contention is whether the accused interconnect’s quality-of-service or flow-control mechanisms constitute a "dropping means" that is "controlled by the interface means" as required by the claim. For the ’449 Patent, a question may be whether the accused system contains distinct or identifiable "communication manager" and "resource manager" entities, or if this functionality is implemented in a distributed manner that falls outside the claim's scope.
    • Technical Questions: The infringement analysis may raise the question of how the accused Arteris FlexNoC technology actually operates. For the ’818 Patent, what evidence does the complaint provide that the accused product "controls transaction completion" specifically through the mechanism of "dropping data" at the interface? For the ’449 Patent, what is the specific process by which the accused products allocate network resources, and does it map to the sequential request-forward-determine-respond-establish steps of Claim 10?

V. Key Claim Terms for Construction

  • For the ’818 Patent:

    • The Term: "dropping means"
    • Context and Importance: This term is central to the core inventive concept of Claim 1. Its construction will be critical in determining whether the flow control or quality-of-service features of the accused interconnect meet this limitation. Practitioners may focus on whether this term requires a dedicated hardware component for dropping data, or if it can be read more broadly on general packet-handling logic.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The abstract describes the invention as comprising "at least one dropping means (DM) for dropping data exchanged by said first and second module" (’818 Patent, Abstract), suggesting a functional definition.
      • Evidence for a Narrower Interpretation: Figure 2 of the patent depicts the "DM" as a distinct block within the network interfaces "ANIP" and "PNIP," which could support an argument that the term requires a specific, structurally-defined component (’818 Patent, Fig. 2; col. 6:46-52).

  • For the ’449 Patent:

    • The Term: "resource manager"
    • Context and Importance: The identity and function of the "resource manager" are essential to the claimed method. The dispute will likely center on whether the accused products contain a component that performs the specific role of determining resource availability in response to a forwarded request.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent describes the resource manager's function as "managing the resources of the network N" and determining "whether the requested connection... is available" (’449 Patent, col. 7:38-39, col. 8:46-49), which could be interpreted functionally.
      • Evidence for a Narrower Interpretation: Figure 3 depicts the "RM" as a distinct block from the "CM" (Communication Manager), suggesting a structurally separate entity that receives a forwarded request. A defendant may argue this requires a separate, identifiable module rather than a distributed or integrated function (’449 Patent, Fig. 3).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendants provide customers and downstream users with data sheets, manuals, development tools, and support services that instruct and encourage them to use the Accused Products in their infringing manner (Compl. ¶¶215, 226). It also alleges contributory infringement, asserting the Accused Products are especially made for an infringing use and are not staple articles of commerce (Compl. ¶220).
  • Willful Infringement: The complaint alleges willful infringement based on Defendants’ purported pre-suit knowledge of the asserted patents. The alleged bases for this knowledge include: (1) Plaintiff’s 2022 litigation against Arteris (an alleged licensor to AMD) and other industry players (Compl. ¶33); (2) AMD’s alleged membership in RPX, which reported on that litigation (Compl. ¶34); and (3) specific instances where the asserted patents were cited during the prosecution of patent applications assigned to Xilinx and/or AMD, in which Defendants' in-house counsel were allegedly involved (Compl. ¶¶118-119, 139).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of claim scope and technical mapping: can the functional blocks described in the patents, such as a "dropping means" (’818 patent) and a "resource manager" (’449 patent), be mapped onto the specific hardware and software architecture of the accused Arteris NoC interconnect as implemented in Defendants' Versal SoCs? The case may turn on whether the accused products achieve similar results through fundamentally different technical operations.
  • A second key question will be the imputation of knowledge for willfulness: the complaint presents multiple, specific allegations of pre-suit knowledge, particularly through citations in Defendants' own patent prosecution files. The court will need to determine whether knowledge held by patent prosecution counsel, or knowledge of litigation involving a third-party technology licensor, can be legally imputed to the corporate defendants to establish the requisite knowledge and intent for willful infringement.
  • A foundational question for liability will be corporate succession: the complaint alleges that AMD, by acquiring Xilinx in 2022, also acquired Xilinx's pre-acquisition knowledge and infringement liability. The extent to which the court accepts this theory of imputed liability will significantly impact the scope of potential damages, particularly for conduct preceding the acquisition date.