DCT

1:25-cv-01649

Network System Tech LLC v. Marvell Semiconductor Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01649, W.D. Tex., 10/14/2025
  • Venue Allegations: Venue is alleged against Marvell Semiconductor, Inc. based on its "regular and established place of business" and acts of infringement in Austin, Texas. Venue is alleged against the foreign Marvell entities based on their status as foreign corporations.
  • Core Dispute: Plaintiff alleges that Defendant’s System-on-a-Chip (SoC) products infringe seven patents related to Network-on-Chip (NoC) technology for managing on-chip data communication.
  • Technical Context: The technology domain is Network-on-Chip (NoC), an architecture for managing communication between numerous processing components on a single semiconductor chip, which is fundamental to the performance of modern complex electronics.
  • Key Procedural History: The complaint alleges that Defendants had pre-suit knowledge of several asserted patents as of December 19, 2022, based on Plaintiff’s prior litigation against Arteris, Inc., a company from which Defendants allegedly license interconnect technology. Knowledge is also alleged through Defendants' membership in the patent risk management firm RPX Corporation. Plaintiff has statutorily disclaimed claims 1 and 3-5 of the '449 patent.

Case Timeline

Date Event
2002-10-08 Priority Date for '818, '449, and '9893 Patents
2004-03-17 Priority Date for '052 Patent
2004-03-26 Priority Date for '849 Patent
2004-05-18 Priority Date for '800 Patent
2005-04-21 Priority Date for '2893 Patent
2008-04-29 U.S. Patent No. 7,366,818 Issues
2008-05-13 U.S. Patent No. 7,373,449 Issues
2009-09-22 U.S. Patent No. 7,594,052 Issues
2009-11-03 U.S. Patent No. 7,613,849 Issues
2010-08-03 U.S. Patent No. 7,769,893 Issues
2011-12-06 U.S. Patent No. 8,072,893 Issues
2011-12-27 U.S. Patent No. 8,086,800 Issues
2022-12-19 Date of Alleged Knowledge via Prior Litigation
2025-10-14 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,366,818 - *“Integrated Circuit Comprising a Plurality of Processing Modules and a Network and Method for Exchanging Data Using Same”*

The Invention Explained

  • Problem Addressed: The patent describes that implementing end-to-end flow control to ensure no data is dropped in an on-chip network is expensive in terms of chip resources (’818 Patent, col. 5:7-14). Conventional bus systems provide direct and immediate status of transactions, but complex network-on-chip systems introduce one-way transfers where the sender is not immediately aware of the receiver's status, creating the risk of buffer overflow (’818 Patent, col. 4:7-13).
  • The Patented Solution: The invention proposes an alternative scheme that allows data to be dropped under certain conditions, such as buffer overflow, rather than relying solely on preventative flow control. It introduces an "interface means" containing a "dropping means" that manages this process. This interface can control the dropping of data and, consequently, control "transaction completion," for instance by creating and sending an error message when data is dropped, thereby informing the sender of the failure (’818 Patent, Abstract; col. 6:50-54).
  • Technical Importance: This approach provides a flexible mechanism to manage on-chip data traffic that can be less resource-intensive than implementing universal, guaranteed-delivery flow control for all transactions (Compl. ¶ 33).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶ 156).
  • The essential elements of claim 1 include:
    • An integrated circuit with a plurality of processing modules on the same chip.
    • A network on chip for providing a connection between a first and second module.
    • The connection supports transactions with outgoing and return messages.
    • At least one "dropping means" for dropping data exchanged between the modules.
    • At least one "interface means" for managing the interface between a module and the network, where the interface means comprises the "dropping means."
    • The "transaction completion can be controlled by the interface means."

U.S. Patent No. 7,373,449 - *“Apparatus and Method for Communicating in an Integrated Circuit”*

The Invention Explained

  • Problem Addressed: As on-chip systems grow in complexity, a "one-size-fits-all" approach to interconnects becomes inefficient. Different communication tasks have different requirements for bandwidth, latency, and reliability, and a static interconnect may fail to utilize network resources effectively (’449 Patent, col. 7:10-25).
  • The Patented Solution: The patent describes a method for dynamically establishing connections with specific, configurable properties. A module requests a connection from a "communication manager," specifying desired properties. This manager forwards the request to a "resource manager," which determines if the network has sufficient resources (e.g., buffer space, bandwidth) to support the requested properties. If resources are available, the connection is established with those specific properties, allowing for more tailored and efficient data transfer (’449 Patent, Abstract; col. 6:40-62).
  • Technical Importance: The invention enables more efficient resource utilization in an on-chip network by allowing communication channels to be configured independently and dynamically based on the specific needs of the communicating modules (Compl. ¶ 48).

Key Claims at a Glance

  • The complaint asserts independent claim 10 (Compl. ¶ 167). Plaintiff has disclaimed claims 1 and 3-5 (Compl. ¶ 44, fn. 23).
  • The essential steps of method claim 10 include:
    • A first module issuing a request for a connection to a "communication manager," the request comprising desired connection properties.
    • The communication manager forwarding the request to a "resource manager."
    • The resource manager determining if a target connection with the desired properties is available.
    • The resource manager responding with the availability to the communication manager.
    • Establishing the target connection based on the available properties.

U.S. Patent No. 7,594,052 - *“Integrated Circuit and Method of Communication Service Mapping”*

  • Technology Synopsis: The patent describes a method for mapping communication requests to network connections based on a "communication service identification," such as a communication thread or an address range (Compl. ¶ 61). This allows a network interface to translate a module's standard communication request into a request for a specific type of network-on-chip connection with appropriate properties (’052 Patent, Abstract).
  • Asserted Claims: The complaint asserts independent claim 6 (Compl. ¶ 178).
  • Accused Features: The network interfaces within the Accused Products that allegedly map communication requests from processing modules to connections on the on-chip network (Compl. ¶¶ 62-63).

U.S. Patent No. 7,613,849 - *“Integrated Circuit and Method for Transaction Abortion”*

  • Technology Synopsis: The patent discloses a "transaction abortion unit" for aborting a transaction that has already been issued by a module (Compl. ¶ 75). The unit receives an abort request, initiates a discard of the transaction (e.g., from a request buffer), and issues a response indicating the success or failure of the abortion attempt (’849 Patent, Abstract; Compl. ¶ 76).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶ 190).
  • Accused Features: The functionality within the Accused Products' network interfaces that allows for the cancellation or abortion of pending data transactions (Compl. ¶¶ 77-78).

U.S. Patent No. 7,769,893 - *“Integrated Circuit and Method for Establishing Transactions”*

  • Technology Synopsis: This patent describes a method using an "address translation unit" within a network interface to handle addressing (Compl. ¶ 90). The unit takes two distinct pieces of information—one identifying the target module(s) and another identifying a specific location within that module (like a memory address)—and arranges them into a single address for network routing (’9893 Patent, Abstract; Compl. ¶ 91).
  • Asserted Claims: The complaint asserts independent claim 4 (Compl. ¶ 202).
  • Accused Features: The address mapping and translation functions within the network interfaces of the Accused Products that allegedly determine the destination module and internal location for a given data transaction (Compl. ¶¶ 92-93).

U.S. Patent No. 8,072,893 - *“Integrated Circuit with Data Communication Network and IC Design Method”*

  • Technology Synopsis: This patent claims a method of designing an integrated circuit. The method involves identifying a communication channel with a data transfer delay exceeding a threshold and, in response, inserting a specific number of data storage elements (M*N) into that channel to introduce a corrective delay, thereby resolving timing issues in the network design (’2893 Patent, Abstract; Compl. ¶¶ 105-106).
  • Asserted Claims: The complaint asserts independent claim 10 (Compl. ¶ 214).
  • Accused Features: The design and manufacturing processes used to create the Accused Products, which allegedly incorporate the patented method of inserting delay elements to manage on-chip timing (Compl. ¶¶ 107-108, 214).

U.S. Patent No. 8,086,800 - *“Integrated Circuit and Method for Buffering to Optimize Burst Length in Networks on Chips”*

  • Technology Synopsis: The patent discloses a system where interconnect modules (wrappers) at both the requesting (master) and responding (slave) ends buffer data. Each wrapper includes a "determination unit" to determine an optimal amount of data to buffer before transferring it as a single, larger burst across the network, based on communication properties like throughput and latency (’800 Patent, Abstract; Compl. ¶¶ 120-121).
  • Asserted Claims: The complaint asserts independent claim 12 (Compl. ¶ 224).
  • Accused Features: The buffering mechanisms within the interconnect modules of the Accused Products that allegedly accumulate data into optimal-sized bursts before transmission across the on-chip network (Compl. ¶¶ 122-123).

III. The Accused Instrumentality

Product Identification

  • The Accused Products are identified as Marvell's System-on-a-Chip (SoC) products and other products incorporating them, including but not limited to the Orion, Kirkwood, Discovery, Armada, Avanta, Storage, Dove, Berlin, and Octeon families (Compl. ¶ 139).

Functionality and Market Context

  • The accused SoCs are complex integrated circuits that incorporate multiple processors, memory units, and other IP blocks onto a single chip (Compl. ¶ 134). The functionality at issue is the intra-SoC communication architecture, specifically the Network-on-Chip (NoC) technology that manages data transfer between these various components (Compl. ¶ 135). The complaint alleges that these SoCs incorporate interconnect technology licensed from Arteris, Inc. or a derivative thereof (Compl. ¶ 137). A table in the complaint lists accused product categories, such as various SoC families (e.g., Orion, Armada, Octeon) that contain network-on-chip technology (Compl. ¶ 139).

IV. Analysis of Infringement Allegations

The complaint references external exhibits containing claim charts for each asserted patent but does not include them in the filing (Compl. ¶ 142). In the absence of these exhibits, the infringement theory is summarized below based on the complaint's narrative allegations.

  • '818 Patent Infringement Allegations

    • The complaint alleges that the Accused Products directly infringe at least claim 1 of the ’818 patent (Compl. ¶ 156). The infringement theory suggests that the network interfaces connecting processing modules to the on-chip network in Marvell's SoCs function as the claimed "interface means" (Compl. ¶ 32). It is alleged that these interfaces possess a mechanism—the claimed "dropping means"—to discard data to manage network traffic and buffer overflows, and that this capability is used to control the completion of data transactions, as required by the claim (Compl. ¶¶ 30-31, 33).

  • '449 Patent Infringement Allegations

    • The complaint alleges that using the Accused Products constitutes infringement of at least method claim 10 of the ’449 patent (Compl. ¶ 167). The theory posits that when one module on an accused SoC initiates communication with another, it performs the claimed method. This allegedly involves the first module sending a request for a connection with desired properties (e.g., bandwidth, latency) to a functional block acting as a "communication manager," which in turn consults a "resource manager" to determine if network resources are available before the connection is established (Compl. ¶¶ 46, 48).

  • Identified Points of Contention:

    • '818 Patent: An issue for the court may be the technical and definitional scope of "dropping means." The analysis may question whether the accused SoCs' buffer management or flow control systems perform the specific, controlled function of "dropping data" to manage "transaction completion" as contemplated by the patent, or if they operate on a different technical principle that falls outside the claim's scope.
    • '449 Patent: A central evidentiary question will be whether the accused products' operation maps onto the specific "communication manager" and "resource manager" architecture required by claim 10. The analysis will likely focus on what evidence the complaint provides that these distinct functional entities exist and interact in the claimed sequence, as opposed to a more integrated or static method of resource allocation.

V. Key Claim Terms for Construction

  • The Term: "dropping means" (from ’818 Patent, claim 1)

    • Context and Importance: This term is central to the inventive concept of the ’818 patent. The infringement analysis will depend on whether the functionality of the accused SoCs' network interfaces can be characterized as a "dropping means." Practitioners may focus on this term because it distinguishes the invention from systems that rely exclusively on end-to-end flow control to prevent data loss.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the invention as an "alternative scheme for transaction completion" where guaranteed delivery is only used "for certain cases" (’818 Patent, col. 6:28-34). This language may support an interpretation where any mechanism that allows for the intentional discarding of data in lieu of guaranteed delivery could qualify.
      • Evidence for a Narrower Interpretation: Claim 1 requires that "transaction completion can be controlled by the interface means" through this dropping capability. Furthermore, the specification describes the "dropping means" as being "adapted to create an error message if data is dropped" (’818 Patent, col. 6:50-52). This may support a narrower construction requiring an active, controlled mechanism that provides feedback, rather than just incidental data loss from unmanaged buffer overflow.

  • The Term: "communication manager" and "resource manager" (from ’449 Patent, claim 10)

    • Context and Importance: These terms define a two-part functional architecture for establishing connections. Plaintiff must demonstrate that the accused method involves distinct entities or processes performing these separate roles in the claimed sequence. The dispute will likely center on whether the accused systems embody this specific architecture.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent describes these elements functionally. Language such as the "communication managing means... forwards the request... to said resource managing means" (’449 Patent, col. 7:40-45) describes functions that could be performed by different software modules or hardware logic blocks, potentially supporting a view that is not tied to a specific physical implementation.
      • Evidence for a Narrower Interpretation: The claim recites a clear sequence: a request goes to the "communication manager," which then "forward[s] the request to a resource manager," which then "determin[es]" availability and "respond[s]" back. This sequential, multi-step process involving two named entities may support a narrower interpretation that the functions cannot be performed by a single, monolithic unit.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement based on Defendants providing customers, OEMs, and end users with products as well as "instructions, data, tools, user guides, technical resources, and technical specifications" that allegedly encourage and instruct them to use the Accused Products in an infringing manner (Compl. ¶¶ 143, 148). The complaint further cites marketing materials and support services directed at U.S.-based customers as evidence of intent to induce (Compl. ¶¶ 147-148).
  • Willful Infringement: The complaint alleges willful infringement based on pre-suit knowledge of the asserted patents. This knowledge is alleged to have been acquired as early as December 19, 2022, through Plaintiff's litigation against Arteris (an alleged technology supplier to Marvell) and other semiconductor companies, and through notifications provided by RPX Corporation, a patent risk management service to which Defendants allegedly subscribe (Compl. ¶¶ 26-27, 151, 164).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of definitional scope: can the term "dropping means," which the ’818 patent links to controlling transaction completion, be construed to cover the general buffer management and data loss mechanisms that may occur in the accused Network-on-Chip architectures, or does it require a more specific, feedback-oriented system as detailed in the patent's embodiments?
  • A key evidentiary question will be one of architectural mapping: does the operational logic of the accused SoCs map onto the distinct, interacting functional blocks recited in claims—such as the "communication manager" and "resource manager" of the ’449 Patent—or will discovery reveal a fundamental mismatch between the patented methods and the accused systems' actual architecture?
  • The allegations of willfulness will turn on a question of imputed knowledge: can Plaintiff establish that Defendants had actual knowledge of the asserted patents and the risk of infringement based on litigation against an industry peer and technology licensor (Arteris) and through membership in a patent-risk monitoring service (RPX), and, if so, does this rise to the level of egregious conduct required for enhanced damages?