DCT
1:25-cv-01838
Vampire Labs LLC v. Advanced Micro Devices Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Vampire Labs, LLC (Texas)
- Defendant: Advanced Micro Devices, Inc. (Delaware)
- Plaintiff’s Counsel: DiNovo Price LLP; Reichman Jorgensen Lehman & Feldberg LLP
- Case Identification: 1:25-cv-01838, W.D. Tex., 11/14/2025
- Venue Allegations: Venue is based on Defendant AMD maintaining regular and established places of business within the Western District of Texas, including multiple large facilities and thousands of employees in Austin.
- Core Dispute: Plaintiff alleges that Defendant’s central processing units (CPUs) and graphics processing units (GPUs) infringe three patents related to fine-grained power gating techniques designed to reduce static power leakage in microprocessors.
- Technical Context: The technology addresses the management of static, or "leakage," power, a persistent issue in modern semiconductors that worsens as transistor dimensions shrink and becomes a dominant source of energy loss.
- Key Procedural History: The complaint alleges that AMD was formally apprised of U.S. Patent No. 9,098,271 during the prosecution of its own patent application in an Office Action dated August 24, 2017, a fact which may be material to the allegations of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2010-04-07 | ’416 Patent Priority Date |
| 2012-02-02 | ’048 Patent Priority Date |
| 2012-02-05 | ’271 Patent Priority Date |
| 2015-08-04 | ’271 Patent Issue Date |
| 2015-08-11 | ’416 Patent Issue Date |
| 2015-12-22 | ’048 Patent Issue Date |
| 2016-01-01 | Alleged launch of infringing GCN 4.0 "Baffin" architecture |
| 2017-08-24 | Date of Office Action allegedly notifying AMD of the ’271 Patent |
| 2025-11-14 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,218,048 - "Individually activating or deactivating functional units in a processor system based on decoded instruction to achieve power saving" (Issued Dec. 22, 2015)
The Invention Explained
- Problem Addressed: As semiconductor transistor sizes shrink, static "leakage" power becomes the dominant form of power loss, even when parts of a chip are idle (Compl. ¶¶29-30). Traditional "coarse-grained" power gating techniques, which disable large blocks of circuitry like entire processor cores, are often based on predictions, leading to inflexibility and performance latency when the blocks must be powered back on (Compl. ¶¶35-36).
- The Patented Solution: The invention proposes a fine-grained power control system where the processor's instruction decoder determines, on an instruction-by-instruction basis, which specific functional units (e.g., a floating-point adder, an integer unit) are required for execution (’048 Patent, col. 1:49-2:21). A power controller then activates only the necessary unit(s) for the minimal number of clock cycles needed, preventing idle units from consuming static power (Compl. ¶¶47, 56).
- Technical Importance: This instruction-level approach aims to provide a more precise and immediate method of power saving compared to higher-level, predictive, or coarse-grained techniques, directly tying power consumption to the immediate computational workload.
Key Claims at a Glance
- The complaint asserts at least Claim 1 (Compl. ¶46).
- Independent Claim 1 requires:
- An instruction decoder configured to decode an instruction.
- A power controller unit coupled to the decoder.
- A first functional unit coupled to the power controller and decoder.
- A plurality of switches coupling the power controller and functional unit, configurable to improve power-up latency by accelerating in-rush current.
- The power controller is configured to determine if the functional unit is needed based on data from the decoder.
- The power controller is configured to activate/deactivate the functional unit accordingly, powering it on for the minimal number of clock cycles needed.
- The functional unit is prevented from incurring static and dynamic power loss when deactivated.
U.S. Patent No. 9,104,416 - "Autonomous microprocessor re-configurability via power gating pipelined execution units using dynamic profiling" (Issued Aug. 11, 2015)
The Invention Explained
- Problem Addressed: The patent addresses the need to optimize power management in a system where different programs or processes have varying computational needs over time. A static power gating configuration may not be efficient for all workloads (Compl. ¶¶36-37).
- The Patented Solution: The invention describes a method of dynamic profiling where a performance monitoring unit collects real-time performance data about a functional unit's usage (’416 Patent, col. 10:43-52). This utilization level is compared to a threshold, and if a condition is met (e.g., low utilization), the system power gates the functional unit. The system stores these profiles in a lookup table, allowing for the reuse of specific power configurations for corresponding processes during a context switch, which limits the time required to re-profile a known process (’416 Patent, col. 6:45-54; Compl. ¶¶74-75).
- Technical Importance: This approach allows the power management system to adapt to the changing demands of different software processes, creating and reusing tailored power profiles to enhance efficiency.
Key Claims at a Glance
- The complaint asserts at least Claim 1 (Compl. ¶62).
- Independent Claim 1 requires a method comprising:
- Using a performance monitoring unit to collect performance data of a functional unit in a processor's execution stage.
- Determining a utilization level of the functional unit based on the performance data.
- Comparing the utilization level with a first threshold.
- When a first condition is satisfied, power gating the functional unit.
- Updating a configuration register that controls a switch governing power to the functional unit.
- Updating a lookup-table (in off-chip or on-chip memory) with information from the configuration register to limit startup time for profiling a current process.
- The lookup-table stores specific needs values for a plurality of processes to permit reuse during each context switch.
U.S. Patent No. 9,098,271 - "Autonomous microprocessor re-configurability via power gating pipelined execution units using static profiling" (Issued Aug. 4, 2015)
- Technology Synopsis: This invention discloses a method where a static code profiler, operating on a developer's machine, analyzes software code to determine which types of functional units will be needed by a target processor. This analysis generates a "specific needs profile" which is then stored on the target processor and used by the operating system to control power gating for that specific program, with the profile being retrieved from a lookup-table during each context switch (’271 Patent, Abstract; col. 2:35-44).
- Asserted Claims: At least Claim 1 (Compl. ¶81).
- Accused Features: The complaint alleges that AMD's developer tools, such as the ROCProfiler and Radeon GPU Profiler, function as the claimed static code profilers for its RDNA GPU architecture (Compl. ¶¶83-84). The output of these tools is alleged to create the specific needs profiles used to manage power gating on the target hardware (Compl. ¶¶86-88).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the accused products as AMD's CPU and GPU product lines, specifically "Zen 3+ and later CPU architectures," "Baffin and later consumer/gaming GPU architectures," and corresponding server/data center architectures (Compl. ¶44). The AMD Ryzen™ 6000 series processors (based on the "Zen 3+" architecture) and processors using the RDNA architecture are identified as illustrative examples (Compl. ¶¶48, 64, 83).
Functionality and Market Context
- The accused products are high-performance microprocessors that allegedly implement "thread-level, fine-grained power gating" to manage power consumption (Compl. ¶¶41, 47). The complaint alleges that AMD's System Management Unit (SMU) acts as a power controller in its CPUs (Compl. ¶52), while its GPUs use performance monitoring units and profiling tools like ROCProfiler to manage power (Compl. ¶¶65, 84). The complaint presents a diagram of the "Zen 3" architecture, showing the distinct instruction decode and execution units relevant to the infringement allegations (Fig. 048-2; Compl. p. 13).
IV. Analysis of Infringement Allegations
’048 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [a] an instruction decoder of a processor...configured to decode an instruction | The Accused Products contain instruction decoders that translate machine code into control signals for the processor's components. | ¶51 | col. 4:62-65 |
| [b] a power controller unit coupled to the instruction decoder | The Accused Products allegedly include a System Management Unit (SMU) that functions as a power controller. | ¶52 | col. 4:3-5 |
| [c] a first functional unit of the processor coupled to the power controller unit and the instruction decoder | The Zen 3+ architecture includes functional units such as Integer and Floating Point Units for executing instructions. A block diagram of the Zen 3 architecture is provided as evidence (Fig. 048-6; Compl. p. 15). | ¶54 | col. 4:5-8 |
| [d] a plurality of switches, the power controller unit and the first functional unit being coupled together via the switches configurable to improve the power up latency...via accelerating in-rush current | The Zen 3+ architecture allegedly uses switches for its fine-grained power gating, coupled to both the power controller (SMU) and the functional units. The complaint cites AMD marketing material on "New SoC-wide Save-restore Acceleration" to support improved latency (Fig. 048-7; Compl. p. 16). | ¶55 | col. 1:49-2:6 |
| [e] wherein the power controller unit is configured to determine whether the first functional unit should be used...based on data of the instruction decoder | The SMU in the Zen 3+ architecture allegedly activates and deactivates functional units based on decoded instructions within execution threads. | ¶56 | col. 8:1-5 |
| [f] wherein the power controller unit is further configured to perform at least one of activating and deactivating the functional unit...and the functional unit is powered on for the minimal number of clock cycles needed | AMD's architecture allegedly controls power for each thread, allowing it to "accurately allocate energy to those parts that need to be operated," implying power is on only when needed (Fig. 048-11; Compl. p. 17). | ¶56 | col. 5:1-10 |
| [g] wherein the first functional unit is prevented from incurring static power loss and dynamic power loss when deactivated | When execution units are power gated, power is turned off, which allegedly prevents them from incurring static power loss. | ¶57 | col. 1:32-35 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether AMD's System Management Unit (SMU), which manages a wide range of power, thermal, and frequency functions for a processor, meets the specific definition of the claimed "power controller unit," which appears to be tightly coupled to the instruction decoder for instruction-by-instruction decisions.
- Technical Questions: The complaint alleges that the SMU makes determinations "based on the decoded instruction stream or thread" (Compl. ¶56). A key factual question will be what evidence demonstrates this level of granularity, as opposed to the SMU making power decisions based on higher-level metrics like overall thread utilization, thermal load, or operating system power states.
’416 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [a] using a performance monitoring unit...collecting performance data of a first type of functional unit in an execution stage | AMD's RDNA processors allegedly incorporate performance monitoring units. The complaint points to the "ROCProfiler" tool as demonstrating the capability to collect performance data from functional units (Fig. 416-1; Compl. p. 20). | ¶65 | col. 10:43-46 |
| [b] determining a utilization level of the first type of functional unit based on the performance data | The RDNA architecture's performance counters allegedly quantify the performance and utilization of components in the computational pipeline. | ¶68 | col. 10:47-49 |
| [c] comparing the utilization level of the first type of functional unit with a first threshold | The complaint alleges that performance optimization using extracted counters "necessarily entials comparing the extracted performance counters to a threshhold of some type." | ¶70 | col. 10:50-52 |
| [d] when a first condition has been satisfied, power gating at least one of the first type of functional unit in the processor | The RDNA architecture is alleged to enable fine-grained power gating, which involves toggling power when defined conditions are met. | ¶72 | col. 10:53-55 |
| [e] updating a configuration register that controls a switch governing power provided to the first functional unit | The complaint alleges the power gating process updates a configuration register, citing a screenshot showing ROCProfiler storing profiling data in a temporary directory/register (Fig. 416-2; Compl. p. 21). | ¶73 | col. 10:56-59 |
| [f] updating a lookup-table...wherein the configuration register is updated using information from the lookup-table during the context switch to limit a startup time required to profile a current process | The complaint alleges the RDNA architecture updates a lookup-table during dynamic profiling and that the register is updated from this table during a context switch. | ¶74 | col. 10:60-65 |
| [g] wherein the lookup-table stores specific needs values for a plurality of processes...to permit reuse...during each context switch | The RDNA architecture allegedly employs a lookup-table to store and reuse specific needs values for different processes. | ¶75 | col. 10:66-11:1 |
- Identified Points of Contention:
- Scope Questions: Does AMD's "ROCProfiler," a developer tool for performance analysis, constitute the claimed "performance monitoring unit" that performs the autonomous control method? The dispute may center on whether the tool is used for runtime, automated power gating decisions or for offline, developer-driven code optimization.
- Technical Questions: The complaint asserts that the accused method involves updating a lookup-table to "limit a startup time required to profile a current process" (Compl. ¶74). A factual question will be whether the evidence shows that the accused products actually use profiling data from one process execution to accelerate the power management decisions for a subsequent execution of the same process after a context switch.
V. Key Claim Terms for Construction
For the ’048 Patent
- The Term: "power controller unit"
- Context and Importance: The infringement theory hinges on equating AMD's System Management Unit (SMU) with the claimed "power controller unit." The scope of this term will be critical. If construed broadly to mean any component that manages power, it may favor the plaintiff's theory. If construed narrowly to require a unit whose primary function is direct, instruction-by-instruction power switching based on decoder output, it could create a more difficult path for proving infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: Claim 1 only requires the unit to be "coupled to the instruction decoder" and "configured to determine" functional unit usage based on decoder data, which may not preclude it from performing other functions.
- Evidence for a Narrower Interpretation: The patent specification describes the power controller in the context of a "logical flow diagram" that appears to operate on a per-instruction basis, checking for specific instruction types (e.g., integer, FP Add) and enabling power for a precise number of clock cycles (’048 Patent, Fig. 7). This embodiment could suggest a more specialized and limited function than a general-purpose SMU.
For the ’416 Patent
- The Term: "updating a lookup-table...to limit a startup time required to profile a current process"
- Context and Importance: This term is central to the claimed invention's efficiency advantage—reusing profiles to avoid re-profiling. Practitioners may focus on this term because the plaintiff's infringement theory must show not only that profiling occurs, but that the results are stored and re-used in a specific way to reduce latency across context switches.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification notes that "a process tailored hardware configuration is stored in a look up table," without necessarily imposing a strict requirement on the mechanism for how this storage limits profiling time (’416 Patent, col. 2:42-44).
- Evidence for a Narrower Interpretation: Claim 1[f] links the lookup-table update to the specific purpose of limiting "a startup time required to profile." This suggests the stored value is not merely a static setting but is part of a dynamic system where profiling would otherwise need to restart, and the lookup-table serves to bypass that restart. The specification's discussion of loading values at each "context switch" supports this narrower, performance-oriented interpretation (’416 Patent, col. 6:49-54).
VI. Other Allegations
- Indirect Infringement: The complaint alleges both induced and contributory infringement for all three patents. The allegations are based on AMD allegedly providing customers with products containing the infringing functionality and instructing them on its use through technical manuals, source code, and other documentation, with the specific intent that customers will implement the infringing fine-grained power gating (Compl. ¶¶58-59, 77-78, 89-90).
- Willful Infringement: The complaint alleges that AMD had pre-suit knowledge of at least the ’271 Patent and its family because it was cited in an Office Action during the prosecution of one of AMD's own patent applications in 2017 (Compl. ¶¶93-94). The complaint alleges that continued infringement after this notice constitutes willful, knowing, and reckless behavior. Post-suit willfulness is also alleged based on the notice provided by the filing of the complaint itself (Compl. ¶92).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core technical issue will be one of mechanism and granularity: Does the evidence show that AMD's power management systems, such as the SMU, make fine-grained, power-gating decisions on a per-instruction basis as required by the ’048 patent, or do they operate based on higher-level heuristics such as overall core utilization and thermal state?
- A key evidentiary question will concern the function of developer tools: Are AMD's profiling tools, such as ROCProfiler, merely instruments for offline developer analysis, or does the complaint successfully demonstrate that they are integrated into an automated, runtime system that dynamically creates and reuses power profiles during context switches, as claimed by the ’416 and ’271 patents?
- A central legal battle will likely focus on willfulness: The complaint's allegation that AMD was cited the ’271 patent during its own patent prosecution presents a specific factual basis for pre-suit knowledge that, if proven, raises a significant question for the court regarding whether AMD’s subsequent conduct was objectively reckless.