Vervain LLC v. SK Hynix Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Vervain, LLC (Texas)
  • Defendant: SK hynix Inc. (Republic of Korea); SK hynix America, Inc. (California); SK hynix NAND Product Solutions Corp. (d/b/a Solidigm) (Delaware); and Solidigm Inc. (Delaware)
  • Plaintiff’s Counsel: McKool Smith, P.C.
• Case Identification: 1:26-cv-00259, W.D. Tex., 02/03/2026
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants maintain a regular and established place of business in the District, citing specific Austin-based employees and office locations involved in sales and support for local customers.
• Core Dispute: Plaintiff alleges that Defendant’s flash memory products, including solid-state drives (SSDs), infringe seven patents related to methods for managing data in hybrid memory systems that combine multi-level cell (MLC) and single-level cell (SLC) non-volatile memory to enhance device lifetime and performance.
• Technical Context: The technology concerns hybrid flash memory architectures that balance the high-density, lower-cost characteristics of MLC memory with the superior speed and endurance of SLC memory, a foundational technique for modern SSDs in consumer and enterprise markets.
• Key Procedural History: The complaint notes that many of the asserted patents were previously or are currently asserted in related litigation against Phison Electronics, Kingston Technology, Micron Technology, and Western Digital. The complaint also alleges that Defendants were aware of at least three of the asserted patents as early as July 8, 2020, pursuant to a standstill agreement between the parties.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,891,298 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 8891298, “Lifetime Mixed Level Non-Volatile Memory System,” issued November 18, 2014 Compl. ¶29

The Invention Explained

• Problem Addressed: The patent addresses the inherent trade-off in flash memory design between lower-cost, high-density Multi-Level Cell (MLC) memory, which has limited write endurance, and more expensive, lower-density Single-Level Cell (SLC) memory, which is faster and significantly more durable (Compl. ¶47; ’300 Patent, col. 1:44-2:4).
• The Patented Solution: The invention describes a memory system with a controller that intelligently manages both MLC and SLC memory modules. The controller performs two primary functions: (1) if data written to an MLC block fails a data integrity test, the controller remaps that data to a more reliable SLC block; and (2) the controller tracks block access frequency and proactively moves frequently written ("hot") data from less-durable MLC blocks to more-durable SLC blocks to extend the overall life of the memory system ’298 Patent, abstract ’298 Patent, col. 6:55-65
• Technical Importance: This hybrid management strategy allows storage device manufacturers to use cheaper MLC flash for the bulk of storage capacity while strategically using a smaller amount of SLC flash to handle write-intensive tasks and mitigate data corruption, thereby improving both performance and device longevity without a proportional increase in cost Compl. ¶47

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶58
• Claim 1 of the ’298 patent recites a system for storing data with the following essential elements:
  • At least one MLC non-volatile memory module.
  • At least one SLC non-volatile memory module.
  • A controller adapted to:
    • maintain an address map for the MLC and SLC modules;
    • determine if a data write to the MLC module fails a data integrity test and, upon failure, remap the corresponding entry to the SLC module;
    • determine the most frequently accessed blocks by maintaining a count; and
    • allocate blocks with the most frequent writes by transferring their contents to the SLC module.
• The complaint reserves the right to identify additional infringing claims during discovery Compl. ¶58

U.S. Patent No. 9,196,385 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 9196385, “Lifetime Mixed Level Non-Volatile Memory System,” issued November 24, 2015 Compl. ¶30

The Invention Explained

• Problem Addressed: As with the related ’298 Patent, this patent addresses the challenge of creating a cost-effective, high-endurance non-volatile memory system by combining the distinct advantages of MLC and SLC flash memory technologies Compl. ¶47 ’300 Patent, col. 1:44-2:4
• The Patented Solution: The invention is structurally similar to that of the ’298 patent but explicitly recites a "flash translation layer (FTL)" as the component adapted to perform the memory management functions. The FTL is responsible for maintaining the address map, remapping data from MLC to SLC upon a data integrity test failure, tracking block access frequency, and allocating frequently written data to the SLC module ’385 Patent, col. 7:12-8:4 The FTL is typically a firmware layer that runs on the memory controller and makes the underlying physical memory appear as a simple block storage device to the host system.
• Technical Importance: By framing the solution in the context of the FTL, the patent aligns with the standard architectural component in SSDs responsible for abstracting the complexities of NAND flash, such as wear-leveling and garbage collection, from the host computer system ’300 Patent, col. 3:1-12

Key Claims at a Glance

• The complaint asserts at least independent claim 1 Compl. ¶103
• Claim 1 of the ’385 patent recites a system for storing data with the following essential elements:
  • At least one MLC non-volatile memory module.
  • At least one SLC non-volatile memory module.
  • A flash translation layer (FTL) adapted to perform the same four functions recited for the controller in claim 1 of the ’298 Patent (maintaining a map, remapping on integrity failure, counting access frequency, and allocating frequent writes to the SLC module).
• The complaint reserves the right to identify additional infringing claims during discovery Compl. ¶103

U.S. Patent No. 9,997,240 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 9997240, “Lifetime Mixed Level Non-Volatile Memory System,” issued June 12, 2018 Compl. ¶31
• Technology Synopsis: This patent describes a memory system controller that allocates frequently written data to "hot blocks" in an SLC module and infrequently written data to "cold blocks" in an MLC module. The system also performs data integrity tests and remaps data from MLC to SLC upon failure, and periodically moves data to SLC based on reaching a predetermined access count value Compl. ¶121
• Asserted Claims: At least independent claim 6 Compl. ¶120
• Accused Features: The complaint alleges that the controllers in the Accused Products perform these functions through their SLC caching, wear-leveling, garbage collection, and error management procedures Compl. ¶¶126-128

U.S. Patent No. 10,950,300 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 10950300, “Lifetime Mixed Level Non-Volatile Memory System,” issued March 16, 2021 Compl. ¶32
• Technology Synopsis: This patent claims a system that includes volatile memory (e.g., DRAM) in addition to SLC and MLC non-volatile memory. A controller performs a data integrity test by retaining a copy of data in the volatile memory after a write operation to the MLC element and then comparing the two. A failure of this test results in remapping the data to a different physical address to enhance endurance Compl. ¶137
• Asserted Claims: At least independent claim 1 Compl. ¶136
• Accused Features: The complaint alleges that the DRAM caches included in the Accused Products are used to retain data during write operations to NAND flash, enabling the controller to perform integrity checks by comparing the data in DRAM with the data stored in the flash memory Compl. ¶¶147-149

U.S. Patent No. 11,830,546 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 11830546, “Lifetime Mixed Level Non-Volatile Memory System,” issued November 28, 2023 Compl. ¶33
• Technology Synopsis: This patent is substantively similar to the ’300 patent, describing a system where a controller uses both its own internal memory and random access volatile memory to perform a data integrity test. It involves reading data back to the controller memory after a write and comparing it to a retained copy to verify integrity, with failures resulting in remapping Compl. ¶162
• Asserted Claims: At least independent claim 1 Compl. ¶161
• Accused Features: The complaint alleges infringement based on the use of controller caches and system RAM in the Accused Products to cache data and perform integrity checks by comparing stored data with retained data Compl. ¶¶169-170

U.S. Patent No. 12,119,054 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 12119054, “Lifetime Mixed Level Non-Volatile Memory System,” issued October 15, 2024 Compl. ¶34
• Technology Synopsis: This patent describes a system where the controller performs a data integrity test during a read operation. If reading stored data from the MLC memory space fails the test, the controller remaps the corresponding logical address entry to an available physical address in the SLC memory element Compl. ¶181
• Asserted Claims: At least independent claim 1 Compl. ¶180
• Accused Features: The complaint points to data refresh and remapping operations in the Accused Products, where controllers perform data integrity tests and move data from MLC to SLC in response to data integrity problems discovered during read operations or background scans Compl. ¶186

U.S. Patent No. 12,224,005 - “Lifetime Mixed Level Non-Volatile Memory System”

• Patent Identification: U.S. Patent No. 12224005, “Lifetime Mixed Level Non-Volatile Memory System,” issued February 11, 2025 Compl. ¶35
• Technology Synopsis: This patent claims an apparatus where a controller writes multi-bit data to a first group of memory cells (MLC). If this group fails a data integrity test, the controller writes the information to a second group of cells using only a single bit per cell (SLC) and remaps the logical address range accordingly Compl. ¶195
• Asserted Claims: At least independent claim 1 Compl. ¶194
• Accused Features: The complaint alleges that the controllers in the Accused Products employ SLC write buffers and caching technology to write data to SLC memory in response to data integrity errors occurring in the MLC memory Compl. ¶199

III. The Accused Instrumentality

Product Identification

• The complaint identifies "Accused Products" as certain flash memory products made, used, or sold by Defendants, including solid-state drives (SSDs) and embedded flash products such as eMMC and UFS Compl. ¶¶3, 10, 52 A non-limiting list of exemplary products is provided, including the SK hynix Silver S32, Gold P31, and Platinum P51, as well as the Solidigm P44 Pro and D7-PS1010 Compl. ¶¶51-52

Functionality and Market Context

• The Accused Products are high-performance storage devices that use non-volatile NAND flash memory managed by a controller chip Compl. ¶51 The complaint alleges these products utilize a hybrid architecture combining high-density memory (such as TLC or QLC, which are types of MLC) with a high-performance/endurance cache operated in SLC mode (referred to as "SLC Caching" or a "pseudo-SLC cache") Compl. ¶¶61, 64, Ex. HH This architecture is designed to improve write speeds and device endurance Compl. ¶11 Compl. ¶¶21-22 The complaint provides a diagram from Phison, a supplier of controllers for some accused products, illustrating the operation where incoming data is written to an "SLC buffer" before being copied to "TLC mode" memory Compl. ¶19, Ex. EE
• The complaint positions Defendants as a "top tier semiconductor supplier" and the "second-largest DRAM and NAND supplier globally," with over $45 billion in annual revenue Compl. ¶¶9, 12 It further alleges that the Accused Products are sold to end users and major electronics manufacturers like Apple, Dell, and Lenovo Compl. ¶13

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,891,298 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A potential point of contention may be whether memory designated as TLC (3 bits per cell) or QLC (4 bits per cell) in the Accused Products falls within the scope of the term "MLC non-volatile memory module" as understood at the time of the invention. Similarly, it raises the question of whether a "pseudo-SLC cache" (where MLC/TLC cells are operated in SLC mode) constitutes an "SLC non-volatile memory module" as required by the claim.
  • Technical Questions: The analysis may turn on the specific mechanism of the "data integrity test" alleged in the complaint. A question for the court could be whether the general-purpose error correction (ECC) monitoring and data refresh functions of the accused controllers perform the specific step of remapping from MLC to SLC in the event of such a failure, as claimed, or if these are distinct, unrelated operations.

U.S. Patent No. 9,196,385 Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: The primary question distinct to this patent is whether the accused functionalities are performed by the "flash translation layer (FTL)" specifically. A potential defense could argue that certain functions (e.g., raw error detection) are handled by dedicated hardware blocks in the controller separate from the FTL firmware that manages address mapping and garbage collection.
  • Technical Questions: The technical questions regarding the "data integrity test" and the nature of the "SLC module" are substantially similar to those identified for the ’298 Patent.

V. Key Claim Terms for Construction

"data integrity test"

• Term: "data integrity test" (from claim 1 of the ’298 and ’385 Patents)
• Context and Importance: This term is central to the infringement theory, as the patents require a remapping from MLC to SLC to occur specifically "in the event of such a failure." The definition will determine what kind of error or event must trigger the remapping. Practitioners may focus on this term because Defendants could argue that their standard error correction or background data scrubbing processes are not the specific "test" contemplated by the patents.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstracts describe the function broadly as determining "if a range of addresses ... fails a data integrity test" without specifying the test's mechanism ’298 Patent, abstract This language may support a construction that covers any process that verifies data correctness, including standard read-after-write checks or monitoring ECC correction levels.
  • Evidence for a Narrower Interpretation: The flow chart in Figure 3B of the patents depicts a specific sequence: "Write combined data" (110), "Read NAND Flash" (112), "Compare Data Written" (114), and a "Match?" decision block (116). This could support a narrower construction limiting the "test" to a direct, post-write comparison rather than a more general background process.

"SLC non-volatile memory module"

• Term: "SLC non-volatile memory module" (from claim 1 of the ’298 and ’385 Patents)
• Context and Importance: The infringement allegations rely on the "SLC Caching" or "pseudo-SLC" features of the Accused Products meeting this limitation. The case may hinge on whether a "module" can be formed by operating MLC/TLC cells in an SLC mode, or if it must be a physically distinct type of memory.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patents focus on the functional characteristics of SLC memory—namely, its superior endurance and faster access speeds—as the reason for its use ’300 Patent, col. 2:25-33 This focus on function rather than physical structure may support construing the term to cover any memory operating with those SLC characteristics.
  • Evidence for a Narrower Interpretation: Figure 4 of the patents depicts a system with structurally distinct banks of "MLC" blocks (60a, 60b) and "SLC" blocks (62a, 62b). This diagram could be used to argue that the claims require physically separate modules, not just different operational modes of the same physical memory cells.

VI. Other Allegations

Indirect Infringement

• The complaint alleges induced infringement against Defendants for selling the Accused Products to third-party computer manufacturers, such as Dell, Apple, and Lenovo Compl. ¶97 Compl. ¶115 The inducement is allegedly based on providing the products along with "direction, instruction, documentation, and other information" that suggests their use in an infringing manner Compl. ¶97

Willful Infringement

• The complaint alleges willful infringement based on pre-suit knowledge of the patents. It specifically claims that Defendants were aware of the ’298, ’385, and ’240 patents "as early as July 8, 2020, when Vervain and SK executed a standstill agreement specifically identifying" those patents Compl. ¶99 For all asserted patents, willfulness is alleged based on Defendants continuing their infringing conduct despite this knowledge, thereby disregarding an objectively high likelihood of infringement Compl. ¶99 Compl. ¶116

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the terms “MLC module” and “SLC module,” which are rooted in the context of physically distinct memory types, be construed to cover the accused products’ use of modern TLC/QLC NAND flash where a portion of the cells are dynamically operated in a “pseudo-SLC” mode?
• A key evidentiary question will be one of causal linkage: does the evidence show that the accused controllers’ data refresh and error correction functions perform the specific sequence required by the claims—namely, remapping data from an MLC area to an SLC area as a direct consequence of a “data integrity test failure”—or are these technologically distinct background maintenance operations?
• A central question for damages will be the impact of alleged pre-suit knowledge: given the complaint’s specific allegation of a 2020 standstill agreement identifying three of the asserted patents, the court will need to examine what knowledge Defendants possessed regarding the technology and whether their subsequent conduct rises to the level of objective recklessness required for a finding of willfulness and potential enhanced damages.