DCT
5:22-cv-00905
InnoMemory LLC v. BROADWAY National Bank
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Innomemory, LLC (Texas)
- Defendant: Broadway National Bank d/b/a Broadway Bank (Texas)
- Plaintiff’s Counsel: Ramey LLP
- Case Identification: 5:22-cv-00905, W.D. Tex., 11/17/2022
- Venue Allegations: Venue is based on Defendant having regular and established places of business within the Western District of Texas where it allegedly committed acts of infringement.
- Core Dispute: Plaintiff alleges that Defendant’s use of computing devices containing industry-standard DDR memory infringes two patents related to power-saving methods for memory read and refresh operations.
- Technical Context: The technology concerns methods for reducing power consumption in Dynamic Random Access Memory (DRAM), a fundamental component in nearly all modern computing devices from servers to automated teller machines (ATMs).
- Key Procedural History: The complaint is a First Amended Complaint. No other significant procedural events, such as prior litigation or administrative challenges to the patents, are mentioned in the complaint.
Case Timeline
| Date | Event |
|---|---|
| 1999-02-13 | U.S. Patent No. 6,240,046 Priority Date |
| 2001-05-29 | U.S. Patent No. 6,240,046 Issue Date |
| 2002-03-04 | U.S. Patent No. 7,057,960 Priority Date |
| 2006-06-06 | U.S. Patent No. 7,057,960 Issue Date |
| 2022-11-17 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,240,046 - "INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE," issued May 29, 2001
The Invention Explained
- Problem Addressed: The patent’s background section describes the trade-off between performance and power consumption in memory devices. It notes that prior art memory which retrieves multiple data words in a single cycle wastes power when only one word is needed (e.g., in random access operations), a significant issue for portable systems (’046 Patent, col. 2:1-15).
- The Patented Solution: The invention is a memory circuit that can operate flexibly, retrieving either a single data word or multiple data words from the memory array in one clock cycle (’046 Patent, Abstract). This dual-mode capability allows the memory to conserve power by retrieving only one word for random reads, while also saving power during sequential "burst" reads by retrieving multiple words simultaneously, thereby reducing the number of times the memory array must be accessed (’046 Patent, col. 2:18-43). The patent discloses using a flip-flop to switch between these two operational states (’046 Patent, col. 2:44-50).
- Technical Importance: The described solution aims to optimize memory power consumption by adapting the data retrieval strategy to the type of memory access request (random vs. burst), a key consideration for improving efficiency in computing systems (’046 Patent, col. 2:58-67).
Key Claims at a Glance
The complaint alleges infringement of one or more unspecified method claims (Compl. ¶14). Representative independent method claim 9 includes the following essential elements:
- A method of reading data from a memory array, comprising:
- retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations; and
- retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations.
- The complaint reserves the right to assert additional claims (Compl. fn. 1, 2).
U.S. Patent No. 7,057,960 - "METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS," issued June 6, 2006
The Invention Explained
- Problem Addressed: The patent addresses power consumption during background "refresh" operations required by DRAMs. In conventional systems, even when only a portion of the memory needs refreshing (e.g., in a low-power standby mode), the support circuits for the entire memory array, or large portions of it, are activated, leading to unnecessary power drain (’960 Patent, col. 1:36-54).
- The Patented Solution: The patent discloses a method for reducing power by dividing the memory array into multiple sections and controlling background operations, such as refresh, on a per-section basis (’960 Patent, Abstract). This is achieved by presenting control and address signals only to the "periphery array circuits" of the specific section(s) undergoing the operation, while leaving the circuits for other sections inactive (’960 Patent, col. 2:40-51). Figure 3 illustrates this sectional control architecture with distinct control signals (REF0-REF3) for different memory quadrants (’960 Patent, Fig. 3).
- Technical Importance: This method aims to significantly lower standby power consumption by minimizing the activity of peripheral support circuitry during refresh cycles, a critical factor for battery-powered and mobile devices (’960 Patent, col. 2:32-38).
Key Claims at a Glance
The complaint alleges infringement of one or more unspecified method claims (Compl. ¶22). Representative independent method claim 1 includes the following essential elements:
- A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
- controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said background operations can be enabled simultaneously in two or more sections independently of any other section; and
- presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
- The complaint reserves the right to assert additional claims (Compl. fn. 3, 4).
III. The Accused Instrumentality
Product Identification
The complaint identifies two categories of accused instrumentalities:
- "Accused DDR Memory": Any memory device that complies with JEDEC industry standards DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5 (Compl. ¶¶ 8, 18).
- "Accused Computing Device": Any computing device used by the Defendant that incorporates the Accused DDR Memory. This includes, but is not limited to, servers, desktop computers, laptops, tablets, and automated teller machines (ATMs) (Compl. ¶¶ 11, 20).
Functionality and Market Context
The infringement allegation is not based on a specific proprietary product but on the standardized functionality of DDR memory, a ubiquitous component in modern electronics (Compl. ¶8). The complaint asserts that the Defendant, Broadway Bank, has "used" these Accused Computing Devices in its operations, including providing laptops to employees and operating servers and ATMs (Compl. ¶¶ 13, 14, 22-25). The complaint lists major technology companies like HP, Lenovo, Dell, IBM, NCR, and Diebold as exemplary vendors of these devices, underscoring the widespread use of the accused technology (Compl. ¶¶ 12, 21).
IV. Analysis of Infringement Allegations
The complaint references but does not attach claim chart exhibits mapping the asserted claims to the accused products (Compl. ¶¶ 9, 19). The following tables summarize the infringement theory against the representative claims identified in Section II, based on the narrative allegations in the complaint.
’046 Patent Infringement Allegations
| Claim Element (from Independent Claim 9) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations | Defendant's use of devices containing Accused DDR Memory, which performs read operations to retrieve single data words from memory. | ¶¶ 8, 14 | col. 2:48-53 |
| and retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations. | Defendant's use of devices containing Accused DDR Memory, which performs "burst read" operations that retrieve multiple sequential data words. | ¶¶ 8, 14 | col. 2:30-43 |
’960 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals... | Defendant's use of devices containing Accused DDR Memory, which performs background refresh operations in what is alleged to be a sectional manner. | ¶¶ 18, 22 | col. 2:40-45 |
| and presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections. | The internal operation of the Accused DDR Memory during refresh cycles, which allegedly directs control signals to activate only the necessary peripheral circuits. | ¶¶ 18, 22 | col. 2:45-51 |
No probative visual evidence provided in complaint.
- Identified Points of Contention:
- ’046 Patent: The analysis may focus on whether the operational modes of JEDEC-compliant DDR memory, particularly its implementation of "burst reads," meet the specific limitations of "retrieving more than one data word...in the read clock cycle" as defined by the patent. The dispute could involve technical details of data retrieval timing and array access within a standard burst operation.
- ’960 Patent: A central question will likely be whether the standardized background refresh mechanisms in Accused DDR Memory practice the claimed method of sectional control. The analysis may turn on whether the JEDEC standards require activating peripheral circuits for only the sections being refreshed, or if standard operation differs in a way that avoids infringement.
V. Key Claim Terms for Construction
Patent: ’046 Patent
- The Term: "retrieving...more than one data words from the memory array in the read clock cycle"
- Context and Importance: This term is central to the patent's claimed power-saving benefit for burst operations. The infringement case against standardized DDR memory will depend on whether its "burst read" feature, a core part of the standard, is construed as meeting this limitation. Practitioners may focus on this term because the dispute will likely involve a technical comparison between the patent's description of a multi-word retrieval and the precise mechanism by which a JEDEC-compliant memory chip outputs sequential data during a burst.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The abstract states the invention is for "retrieving more than one data word in a clock cycle where the memory array is accessed" to save power in burst requests, suggesting a functional definition tied to reducing array accesses (’046 Patent, Abstract).
- Evidence for a Narrower Interpretation: The specification describes a specific implementation where "two 36-bit words can be retrieved from the memory array in the first cycle," which could be argued to limit the scope to simultaneous retrieval of a specific number of words, rather than any sequential output characteristic of a burst read (’046 Patent, col. 2:36-38).
Patent: ’960 Patent
- The Term: "controlling the background operations in one or more sections"
- Context and Importance: This term is the foundation of the infringement allegation for the ’960 patent. The case depends on whether the standard refresh operations of Accused DDR Memory can be characterized as "controlling" operations in discrete "sections." Practitioners may focus on this term because the defense could argue that standard refresh protocols operate on a bank or row basis, which may not align with the patent's specific disclosure of sectional control via dedicated periphery circuits.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The summary of the invention frames the goal broadly as reducing power consumption by controlling operations in "one or more sections" to avoid activating unnecessary support circuits, suggesting the term applies to any method achieving this functional result (’960 Patent, col. 2:40-51).
- Evidence for a Narrower Interpretation: The detailed description and figures show a specific architecture with four distinct quadrants (QUAD0-QUAD3) and corresponding control signals (REF0-REF3) that enable or disable the periphery circuits for each one (’960 Patent, Fig. 3; col. 4:5-14). This could support an argument that "controlling...in...sections" requires this explicit, partitioned architecture.
VI. Other Allegations
- Indirect Infringement: The complaint makes no direct allegations of induced or contributory infringement but includes footnotes reserving the right to add such claims if discovery reveals supporting facts (Compl. fn. 1, 3).
- Willful Infringement: The complaint does not allege willful infringement based on pre-suit knowledge. It explicitly reserves the right to amend the complaint to add claims for willfulness should discovery reveal such knowledge (Compl. fn. 1, 3).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue for both patents will be one of technical mapping: do the highly standardized, JEDEC-defined operations for "burst reads" (’046 Patent) and "refresh cycles" (’960 Patent) in commodity DDR memory practice the specific methods recited in the asserted claims, or is there a fundamental mismatch in their technical implementation?
- The case will also depend on claim scope: can claim terms rooted in the patents’ specific embodiments, such as "retrieving...in the read clock cycle" and "controlling...in...sections," be construed broadly enough to cover the functional equivalents allegedly present in industry-standard memory, or will they be limited to the particular circuit architectures disclosed?