DCT

5:22-cv-00909

InnoMemory LLC v. Lone Star National Bank

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 5:22-cv-00909, W.D. Tex., 08/18/2022
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendant maintaining regular and established places of business within the Western District of Texas, including several specified addresses in San Antonio.
  • Core Dispute: Plaintiff alleges that Defendant’s use of computing devices containing industry-standard Double Data Rate (DDR) memory infringes patents related to power-saving methods in random access memory circuits.
  • Technical Context: The technology domain is semiconductor memory, specifically architectures for Dynamic Random Access Memory (DRAM) that reduce power consumption during read and refresh operations, which is a critical feature for both high-performance and mobile computing.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
1999-02-13 U.S. Patent No. 6,240,046 Priority Date
2001-05-29 U.S. Patent No. 6,240,046 Issue Date
2002-03-04 U.S. Patent No. 7,057,960 Priority Date
2006-06-06 U.S. Patent No. 7,057,960 Issue Date
2022-08-18 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - “INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE”

The Invention Explained

  • Problem Addressed: The patent’s background section describes an "unfilled need for memory devices with low power consumption characteristics," noting that prior art memory architectures optimized for multi-word "burst" reads waste power when performing single-word "random" reads by unnecessarily accessing additional data that is then discarded (’046 Patent, col. 2:8-15).
  • The Patented Solution: The invention discloses a random access memory circuit that can operate in different modes to improve power efficiency (’046 Patent, Abstract). It is capable of retrieving a single data word from the memory array in one clock cycle for random read requests, and alternatively retrieving more than one data word in a single clock cycle for burst read requests, thereby avoiding the power waste associated with fixed-width memory accesses (’046 Patent, col. 2:45-56). The specification explains that while retrieving two words uses approximately 20% more power than one, doing so for a burst read avoids a second full memory access, resulting in an overall power usage of only 60% compared to two separate single-word reads (’046 Patent, col. 3:6-23).
  • Technical Importance: This approach provided a method for making DRAMs more power-efficient by adapting their internal operation to different data access patterns, a significant consideration for the expanding market of portable, battery-powered computing systems (’046 Patent, col. 2:11-13).

Key Claims at a Glance

  • The complaint asserts infringement of one or more of claims 1-19 (Compl. ¶12). Independent claims 1, 9, and 15 are identified in the patent.
  • Claim 1 (Independent): An integrated circuit random access memory comprising:
    • a memory array capable of storing a plurality of data words; and
    • a data bus coupled to the memory array, the data bus having a width of more than one data word;
    • wherein the random access memory integrated circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first clock cycle...
  • The complaint does not specify assertion of any dependent claims but reserves the right to amend its allegations (Compl. fn. 1).

U.S. Patent No. 7,057,960 - “METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS”

The Invention Explained

  • Problem Addressed: The patent addresses power consumption during standby or reduced power modes in devices using DRAM (’960 Patent, col. 1:39-44). Conventional DRAMs activate periphery circuits for all memory sections (e.g., quadrants) during a refresh operation, even if only a portion of the memory array is being refreshed, leading to unnecessary power draw (’960 Patent, col. 2:25-29).
  • The Patented Solution: The patent describes a method for reducing power consumption by controlling background operations, such as refresh, on a sectional basis within the memory array (’960 Patent, Abstract). The invention presents control signals and decoded addresses only to the peripheral array circuits of the specific section(s) being refreshed, while leaving the circuits for other sections inactive (’960 Patent, col. 2:58-64).
  • Technical Importance: The invention offered a way to lower standby power consumption in memory devices, a critical requirement for battery-powered portable terminals and other mobile electronics (’960 Patent, col. 2:30-33).

Key Claims at a Glance

  • The complaint asserts infringement of one or more of claims 1-27 (Compl. ¶20). Independent claims 1, 9, and 27 are identified in the patent.
  • Claim 1 (Independent): A method for reducing power consumption during background operations in a memory array with a plurality of sections, comprising the steps of:
    • controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
    • presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
  • The complaint does not specify assertion of any dependent claims but reserves the right to amend its allegations (Compl. fn. 3).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are computing devices, including servers, desktop computers, laptops, tablets, and automated teller machines (ATMs), that Defendant has allegedly used (Compl. ¶10, ¶18, ¶20-23).

Functionality and Market Context

  • These computing devices are accused of infringement because they contain "Accused DDR Memory" (Compl. ¶10, ¶18). This memory is defined as any device that complies with JEDEC industry standards DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5 (Compl. ¶8, ¶16). The complaint alleges that Defendant, a community bank, has owned and operated these devices in the course of its business (Compl. ¶2, ¶12, ¶20). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint states that support for its infringement allegations may be found in attached exemplary claim charts (Exhibits B, C, and E), but these exhibits were not provided with the complaint document (Compl. ¶9, ¶17). The complaint’s narrative sections do not provide sufficient detail for a claim-by-claim analysis of the infringement theory.

The core of the infringement allegation appears to be that computing devices containing memory compliant with various JEDEC DDR standards inherently practice the methods and comprise the structures claimed in the patents-in-suit (Compl. ¶8, ¶10, ¶16, ¶18).

  • Identified Points of Contention:
    • Technical Questions: A primary technical question will be whether the mandatory and optional features of the specified JEDEC DDR standards, when implemented, necessarily meet all limitations of the asserted claims. For the ’046 Patent, this raises the question of whether the prefetch architectures inherent to DDR memory perform the claimed function of selectively retrieving one or more data words in the manner described. For the ’960 Patent, a key question is whether standard DDR refresh modes (e.g., Per-Bank Refresh) meet the claim limitations for controlling background operations in discrete "sections" by selectively activating peripheral circuits.
    • Scope Questions: The dispute may center on whether the term "sections" as used in the ’960 Patent can be construed to read on the "banks" of a standard DDR memory architecture. Similarly, for the ’046 Patent, a scope question is whether the claim term "retrieving" can be construed to cover the internal data fetching operations of a DDR prefetch buffer, or if it requires a narrower interpretation tied to external data presentation.

V. Key Claim Terms for Construction

  • Term (’046 Patent): "retrieving a first data word ... in a first clock cycle and a second data word ... in a second clock cycle"

  • Context and Importance: This term is central to the infringement analysis for the ’046 Patent, as Plaintiff’s theory likely relies on mapping the internal prefetch operations of DDR memory—where multiple words are fetched from the array to fill a buffer for subsequent high-speed output—to this "retrieving" language. The definition will determine if an internal architectural feature of a standard-compliant product meets the claim limitation.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The claim uses the general term "retrieving" without specifying whether the retrieval is from the memory array to an internal buffer or to an external pin. This lack of specificity may support an interpretation covering internal memory operations.
    • Evidence for a Narrower Interpretation: The patent’s summary emphasizes a system that "saves power over retrieving more than one data word" for random reads, and where a flip-flop selects between retrieving one word or more than one word (’046 Patent, Abstract; col. 2:45-56). This context, which links the retrieval mode to the type of read request (random vs. burst) for power savings, may support a narrower construction tied to an explicit, selectable mode of operation rather than a fixed prefetch architecture.

  • Term (’960 Patent): "controlling said background operations in each of said plurality of sections ... independently of any other section"

  • Context and Importance: This term is critical because the infringement case for the ’960 Patent likely equates the standard "banks" of a DDR memory device with the claimed "sections." Practitioners may focus on whether the control of refresh operations in one bank is truly "independent" of others in the manner required by the claim.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent discloses controlling background operations in "one or more sections" to reduce power, which could be argued to generically describe any architecture that does not activate the entire array for every operation (’960 Patent, col. 2:52-58).
    • Evidence for a Narrower Interpretation: The background discusses refreshing "one wordline in each of the four quadrants" simultaneously during a refresh cycle, which may suggest that "sections" refers to a specific architectural division like quadrants, which could differ from the bank structure and refresh protocols (e.g., per-bank refresh) of accused DDR devices (’960 Patent, col. 2:19-21).

VI. Other Allegations

  • Indirect Infringement: The complaint pleads only direct infringement but expressly reserves the right to amend its complaint to add claims for indirect infringement pending discovery (Compl. fn. 1-4).
  • Willful Infringement: The complaint does not currently allege willful infringement but reserves the right to add such claims if discovery reveals pre-suit knowledge of the alleged infringement (Compl. fn. 1-4).

VII. Analyst’s Conclusion: Key Questions for the Case

The resolution of this case will likely depend on the court’s determination of the following open questions:

  • A core issue will be one of technical mapping: Do the prefetch and refresh functionalities defined by the JEDEC standards for DDR memory—which are designed primarily for performance—perform the specific power-saving functions recited in the asserted claims, or is there a fundamental mismatch between the standardized operations and the patented inventions?
  • A central legal question will be one of claim scope: Can claim terms rooted in the patents’ specific disclosures, such as "sections" (’960 Patent) and the functional act of "retrieving" data in selectable widths (’046 Patent), be construed broadly enough to cover the distinct architectural constructs and fixed operational modes of industry-standard memory devices?