DCT
6:19-cv-00273
PACT XPP Schweiz AG v. Intel Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: PACT XPP Schweiz AG (Switzerland)
- Defendant: Intel Corporation (Delaware)
- Plaintiff’s Counsel: Haley & Olson, P.C.; Mann | Tindel | Thompson
- Case Identification: 6:19-cv-00273, W.D. Tex., 04/23/2019
- Venue Allegations: Venue is alleged to be proper in the Western District of Texas because Intel maintains a regular and established place of business in the district and has committed alleged acts of infringement there.
- Core Dispute: Plaintiff alleges that Defendant’s multi-core processors and associated technologies infringe twelve patents related to multi-core computer architecture, including bus systems, cache management, clock frequency control, and die stacking.
- Technical Context: The technology at issue concerns fundamental aspects of multi-core processor architecture, a critical domain for determining performance and efficiency in modern computing, from consumer devices to enterprise servers.
- Key Procedural History: The complaint alleges that Defendant had actual knowledge of its infringement of several of the asserted patents prior to this lawsuit, based on the service of a complaint in a prior case, PACT XPP Schweiz AG v. Intel Corporation, 1:19-cv-00267 (DED). This allegation is central to the claims of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 1999-02-25 | U.S. Patent No. 8,471,593 Priority Date |
| 2000-06-13 | U.S. Patent No. 8,301,872 Priority Date |
| 2000-06-13 | U.S. Patent No. 9,250,908 Priority Date |
| 2001-03-05 | U.S. Patent No. 8,312,301 Priority Date |
| 2001-03-05 | U.S. Patent No. 9,075,605 Priority Date |
| 2001-03-05 | U.S. Patent No. 9,552,047 Priority Date |
| 2001-06-20 | U.S. Patent No. 9,170,812 Priority Date |
| 2001-07-17 | U.S. Patent No. 8,819,505 Priority Date |
| 2001-09-03 | U.S. Patent No. 9,037,807 Priority Date |
| 2001-09-03 | U.S. Patent No. 9,436,631 Priority Date |
| 2001-09-19 | U.S. Patent No. 8,686,549 Priority Date |
| 2002-09-06 | U.S. Patent No. 7,928,763 Priority Date |
| 2008-01-01 | Accused Turbo Boost-enabled processors manufactured |
| 2011-01-01 | Accused Sandy Bridge architecture released |
| 2011-01-01 | Accused Turbo Boost 2.0 introduced |
| 2011-04-19 | U.S. Patent No. 7,928,763 Issued |
| 2012-10-30 | U.S. Patent No. 8,301,872 Issued |
| 2012-11-13 | U.S. Patent No. 8,312,301 Issued |
| 2013-06-25 | U.S. Patent No. 8,471,593 Issued |
| 2014-04-01 | U.S. Patent No. 8,686,549 Issued |
| 2014-08-26 | U.S. Patent No. 8,819,505 Issued |
| 2015-05-19 | U.S. Patent No. 9,037,807 Issued |
| 2015-07-07 | U.S. Patent No. 9,075,605 Issued |
| 2015-10-27 | U.S. Patent No. 9,170,812 Issued |
| 2016-01-01 | Accused Turbo Boost Max 3.0 introduced |
| 2016-02-02 | U.S. Patent No. 9,250,908 Issued |
| 2016-09-06 | U.S. Patent No. 9,436,631 Issued |
| 2017-01-01 | Accused mesh bus architecture introduced |
| 2017-01-24 | U.S. Patent No. 9,552,047 Issued |
| 2018-12-01 | Intel announces Foveros technology |
| 2019-01-01 | Intel announces Lakefield product |
| 2019-04-23 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,928,763 - "Multi-Core Processing System," issued Apr. 19, 2011
The Invention Explained
- Problem Addressed: The patent’s background section describes the limitations of traditional processor architectures when executing complex, data-intensive algorithms that may benefit from both parallel and sequential processing methodologies (’763 Patent, col. 1:18-24). The complaint frames this as the challenge of moving and accessing data efficiently in a multi-core system (Compl. ¶9).
- The Patented Solution: The invention proposes a reconfigurable data processing architecture composed of "function cell means" (e.g., ALUs) and "memory cell means" (e.g., RAM) (’763 Patent, Abstract). A key aspect is the formation of "function cell-memory cell combinations" where a function cell manages a control connection to an associated memory cell, enabling the execution of sequencer-like operations within a broadly parallel architecture (’763 Patent, col. 2:18-32; Fig. 2a).
- Technical Importance: This architectural approach sought to combine the efficiency of traditional sequential processors for certain tasks with the high throughput of parallel processing systems, addressing a core challenge in the design of versatile multi-core processors (Compl. ¶8-9).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶38).
- Essential elements of Claim 1 include:
- A multi-processor chip, comprising:
- a plurality of data processing cells, each adapted for sequentially executing functions and having specific components (ALU, data register file, etc.);
- a plurality of memory cells;
- at least one interface unit;
- at least one Memory Management Unit (MMU); and
- a bus system adapted for programmably interconnecting the various cells and units at runtime.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 8,301,872 - "Pipeline Configuration Protocol and Configuration Unit Communication," issued Oct. 30, 2012
The Invention Explained
- Problem Addressed: The patent background describes the technical challenge of managing data communication in a multi-processor system that contains multiple levels of cache memory, an architecture that requires efficient protocols for sharing data between different processor cores (’872 Patent, col. 1:20-33).
- The Patented Solution: The invention claims a microprocessor chip with a multi-level cache system. A "first cache level" (e.g., L1/L2) is dedicated to a specific processor core, while at least one "superior cache level" (e.g., L3/LLC) includes multiple cache nodes that are shared among the processor cores via a bus system (’872 Patent, Abstract; Fig. 1). These shared cache nodes are capable of relaying data between different segments of the bus system, facilitating inter-core communication (’872 Patent, col. 1:49-58).
- Technical Importance: This architecture provides a structured and scalable method for managing data access and coherency between multiple processor cores and a shared, higher-level cache, a design pattern that became central to modern high-performance CPUs (Compl. ¶10).
Key Claims at a Glance
- The complaint asserts independent claim 2 (Compl. ¶62).
- Essential elements of Claim 2 include:
- A microprocessor chip comprising a plurality of processor cores;
- a cache system with multiple levels, including a first dedicated level and a superior shared level with multiple cache nodes;
- a bus system with segments interconnecting the cores and shared cache nodes;
- wherein the first cache level is dedicated to a specific core;
- each shared cache node is communicatively connectable to each core via the bus;
- the highest cache level connects to a higher level memory; and
- each shared cache node connects to at least two bus segments and is capable of both relaying data between those segments and transmitting data between its internal memory and the segments.
- The complaint does not explicitly reserve the right to assert dependent claims for this patent.
U.S. Patent No. 8,312,301 - "Methods and Devices for Treating and Processing Data," issued Nov. 13, 2012
- Technology Synopsis: This patent relates to a processor device with multiple data processing elements (cores) and software for managing the distribution of code sections to subsets of those elements. The technology involves assigning different clock frequencies to different groups of cores executing different code sections, a method for balancing performance and power efficiency (Compl. ¶89-94).
- Asserted Claims: Independent claim 10 (Compl. ¶89).
- Accused Features: Intel processors with the Turbo Boost feature, specifically Turbo Boost Max Technology 3.0 (Compl. ¶88, ¶92-93).
U.S. Patent No. 8,471,593 - "Logic Cell Array and Bus System," issued Jun. 25, 2013
- Technology Synopsis: This patent describes a data processor on a chip with multiple processing cores and a bus system for interconnecting the cores with memory units and an interface. The bus system includes distinct structures for data transfer in at least two directions, and each core has a dedicated connection to an assigned memory unit, which is also accessible by other cores via a secondary bus path (Compl. ¶112-119).
- Asserted Claims: Independent claim 1 (Compl. ¶112).
- Accused Features: Intel Core, Xeon, and Celeron processors with a ring bus system (or equivalents) (Compl. ¶111, ¶117-118).
U.S. Patent No. 8,686,549 - "Reconfigurable Elements," issued Apr. 1, 2014
- Technology Synopsis: This patent relates to a processor device comprising at least two stacked dies. The device includes an interconnect structure with switches, with programmable data processing units implemented on a first die and at least parts of the interconnect structure implemented on a second die (Compl. ¶136-144).
- Asserted Claims: Independent claim 39 (Compl. ¶136).
- Accused Features: Intel chips and chiplets implementing Foveros 3D packaging technology, such as the Lakefield product (Compl. ¶135, ¶138).
U.S. Patent No. 8,819,505 - "Data Processor Having Disabled Cores," issued Aug. 26, 2014
- Technology Synopsis: This patent describes an integrated circuit data processor with a plurality of data processing cores arranged in columns. The invention addresses manufacturing defects by implementing more cores than are intended to be used, allowing defective cores identified during a chip test to be exempted from data transfer via the bus system (Compl. ¶161-167).
- Asserted Claims: Independent claim 27 (Compl. ¶161).
- Accused Features: Intel multi-core processors, particularly Accused Xeon Processors, where certain cores are allegedly turned off due to manufacturing defects (Compl. ¶160, ¶165, ¶167).
U.S. Patent No. 9,037,807 - "Processor Arrangement on a Chip Including Data Processing, Memory, and Interface Elements," issued May 19, 2015
- Technology Synopsis: This patent describes a multi-processor system on a chip where data processing elements (cores), memory elements (LLC slices), and an interface element (System Agent) are interconnected by a bus system. The bus system is adapted to form at least one ring via interconnection elements that include pipeline-registers (Compl. ¶184-191).
- Asserted Claims: Independent claim 1 (Compl. ¶184).
- Accused Features: Intel Core, Xeon, and Celeron processors that include a ring bus system (or equivalents) (Compl. ¶183, ¶189).
U.S. Patent No. 9,075,605 - "Methods and Devices for Treating and Processing Data," issued Jul. 7, 2015
- Technology Synopsis: This patent describes a method for operating a multiprocessor system by dynamically adjusting the clock frequency of at least part of the system. The frequency is first set to a minimum based on the pending operations of a first processor, then increased to a maximum based on the operations of a second processor, and subsequently reduced based on a temperature threshold (Compl. ¶208-213).
- Asserted Claims: Independent claim 1 (Compl. ¶208).
- Accused Features: Intel processors with the Turbo Boost feature (Accused Turbo Boost Instrumentalities) (Compl. ¶207, ¶209).
U.S. Patent No. 9,170,812 - "Data Processing System Having Integrated Pipelined Array Data Processor," issued Oct. 27, 2015
- Technology Synopsis: This patent describes an integrated circuit with a data processor core and at least one array data processor (e.g., a graphics processor). A multi-level cache is shared between the core and the array processor, and a separate instruction dispatch unit sends software threads to the array processor for parallel execution (Compl. ¶230-235).
- Asserted Claims: Independent claim 12 (Compl. ¶230).
- Accused Features: Intel Core, Xeon, and Celeron processors with integrated graphics (Compl. ¶229, ¶231).
U.S. Patent No. 9,250,908 - "Multi-Processor Bus and Cache Interconnection System," issued Feb. 2, 2016
- Technology Synopsis: This patent describes a system with a plurality of processors, a separated cache (e.g., LLC), and a bus system connecting them. The processors, interface, and cache have module identifications (IDs), and the interface transmits data using a protocol that includes the IDs of the sender and receiver (Compl. ¶252-258).
- Asserted Claims: Independent claim 4 (Compl. ¶252).
- Accused Features: Intel Core, Xeon, and Celeron processors with a ring bus system that interconnects cores, LLC slices, and a System Agent (Compl. ¶251, ¶256).
U.S. Patent No. 9,436,631 - "Chip Including Memory Element Storing Higher Level Memory Data on a Page by Page Basis," issued Sep. 6, 2016
- Technology Synopsis: This patent describes a bus system for a multiprocessor system with a plurality of bus segments for each processor. A communication link between a sender and receiver is established based on the executed algorithm, and an identifier is transmitted with the data to identify the source and/or target of the data transfer (Compl. ¶278-282).
- Asserted Claims: Independent claim 1 (Compl. ¶278).
- Accused Features: Intel Core, Xeon, and Celeron processors with a ring bus system (Compl. ¶277, ¶279).
U.S. Patent No. 9,552,047 - "Multiprocessor Having Runtime Adjustable Clock and Clock Dependent Power Supply," issued Jan. 24, 2017
- Technology Synopsis: This patent describes a multiprocessor system where the clock frequency of some data processing units is adjustable at runtime without affecting others. The system also includes a voltage supply adapted to provide higher supply voltages for data processing at higher clock frequencies (Compl. ¶299-306).
- Asserted Claims: Independent claim 1 (Compl. ¶299).
- Accused Features: Intel processors with the Turbo Boost feature, which allegedly uses an integrated voltage regulator (Compl. ¶298, ¶301, ¶305).
III. The Accused Instrumentality
Product Identification
- The accused products are broadly defined as Intel Core processors (including i3, i5, i7, i9), Intel Xeon processors, and Intel Celeron processors that incorporate microarchitectures from Sandy Bridge (released 2011) onwards (Compl. ¶32-34). Specific technologies called out as "accused instrumentalities" include processors with Turbo Boost and those implementing Foveros 3D stacking technology (Compl. ¶35, ¶88, ¶135).
Functionality and Market Context
- The complaint alleges that these processors implement a "ring-based interconnect" or its equivalents (such as a "mesh bus architecture") to facilitate communication between processor cores, integrated graphics, and a shared Last Level Cache (LLC) (Compl. ¶10, ¶45). A diagram titled "Sandy Bridge: Overview" is provided to illustrate this architecture, showing multiple "Core" blocks connected to "LLC" blocks via an internal bus (Compl. p. 4).
- The "Turbo Boost" technology is alleged to dynamically adjust the clock frequencies of individual processor cores to accelerate performance for peak loads while managing power consumption (Compl. ¶12, ¶18).
- The "Foveros" technology is described as a 3D packaging technique that stacks multiple silicon dies, including an "Active Interposer," to connect processing units on different layers (Compl. ¶13-14, ¶138). A marketing graphic for "FOVEROS TECHNOLOGY" depicts this 3D face-to-face chip stacking (Compl. p. 43).
- The complaint asserts that Intel holds over an 80% market share in computer processors and that the accused architectures have been incorporated into the majority of its processor families since 2011, generating tens of billions of dollars in revenue (Compl. ¶3, ¶11).
IV. Analysis of Infringement Allegations
- 7,928,763 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A multi-processor chip, comprising | The accused products are multi-core processors and therefore a multi-processor chip. | ¶39 | col. 13:1-2 |
| a plurality of data processing cells, each adapted for sequentially executing at least one of algebraic and logic functions and having at least one arithmetic logic unit... and other components | The accused processors include a plurality of cores, each containing multiple ALUs, registers, an instruction pointer, and decoders. | ¶40-41 | col. 13:3-11 |
| a plurality of memory cells | The accused processors include Last Level Caches (LLCs). | ¶42 | col. 13:12 |
| at least one interface unit | The accused processors include a System Agent. | ¶43 | col. 13:13 |
| at least one Memory Management Unit (MMU) | The accused processors include memory management functionalities. | ¶44 | col. 13:14-15 |
| a bus system for interconnecting the plurality of data processing cells, the plurality of memory cells, and the at least one interface unit... adapted for programmably interconnecting at runtime... | The accused processors include a ring bus system (or equivalents) that interconnects the cores, LLCs, and the interface unit. | ¶45 | col. 13:16-24 |
- 8,301,872 Patent Infringement Allegations
| Claim Element (from Independent Claim 2) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A microprocessor chip comprising: a plurality of processor cores | The accused products are multi-core processors. | ¶63 | col. 10:1-2 |
| a cache system including multiple levels, including at least (a) a first cache level... and (b) at least one superior cache level including a plurality of same level cache nodes each including an internal cache memory | The accused processors include multiple cache levels (L1, L2, LLCs), with the LLCs constituting a superior level with multiple nodes, each with internal memory. | ¶64, ¶66 | col. 10:3-9 |
| a bus system | The accused processors include a ring bus system or its equivalents. | ¶67 | col. 10:10 |
| wherein: for each of at least one of the plurality of processor cores, a respective cache of the first cache level is assigned and dedicated to the respective processor core... | Each processor core in the accused products includes at least one first-level cache that is dedicated to that core exclusively. | ¶68 | col. 10:12-16 |
| the bus system includes segments interconnecting, at least one of directly and indirectly, at least the plurality of same level cache nodes (i) to each other and (ii) to the plurality of processor cores | The ring bus in the accused products includes segments that interconnect the LLCs to each other and to the processor cores. | ¶69 | col. 10:17-22 |
| each of the plurality of same level cache nodes is communicatively connectable with each of the plurality of processor cores via the bus system for transferring data... | Each LLC in the accused products is connectable with each core via the ring bus for data transmission. | ¶70 | col. 10:23-28 |
| a highest of the multiple levels is connected to a higher level memory | The LLCs in the accused products are connected to higher-level memory such as RAM. | ¶71 | col. 10:29-30 |
| each of the plurality of same level cache nodes is connected to at least two segments of the bus system and is capable of (i) relaying data from a first...to a second...and (ii) transmitting data... | Each LLC in the accused products is allegedly connected to at least two segments of the ring bus and is capable of relaying and transmitting data. | ¶72 | col. 10:31-39 |
- Identified Points of Contention:
- Scope Questions: A central question for the ’763 Patent may be whether the term "programmably interconnecting at runtime," as described in the context of a reconfigurable architecture, can be construed to read on the accused ring bus. The analysis may explore whether this term requires the ability to alter the physical bus topology at runtime, or if dynamic arbitration of traffic on a fixed bus topology is sufficient.
- Technical Questions: For the ’872 Patent, a key technical question is what evidence the complaint provides that the accused LLCs perform the specific function of "relaying data from a first one of the segments... to a second one," as required by the claim. The dispute may focus on whether the LLCs function as active relays for inter-segment communication or primarily as shared data endpoints for the cores.
V. Key Claim Terms for Construction
Term from '763 Patent, Claim 1: "programmably interconnecting at runtime"
- Context and Importance: The infringement reading for the ’763 Patent hinges on whether Intel's ring bus architecture meets this limitation. Practitioners may focus on this term because the patent's specification describes highly flexible, reconfigurable architectures, whereas the accused products utilize a more structured, though dynamically managed, interconnect.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification's discussion of reconfigurable data processing architectures and variable interconnections during run time could support a broad definition covering any non-static data path establishment (’763 Patent, col. 1:25-31).
- Evidence for a Narrower Interpretation: The patent’s detailed description of "function cell-memory cell combinations" and its focus on creating sequencer-like structures within a VPU may suggest the term implies a deeper level of reconfigurability than the traffic management on a fixed-path ring bus (’763 Patent, col. 2:18-32).
Term from '872 Patent, Claim 2: "relaying data"
- Context and Importance: This term is critical as it defines a specific function of the shared "superior" cache nodes. The infringement analysis will depend on whether the accused LLCs are shown to perform this active relaying function between different segments of the ring bus, as opposed to simply serving as a shared memory resource.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent states that the "bus system" facilitates data transfer and that the cache nodes are interconnected by this bus system, which could be argued to mean any role in moving data on the bus constitutes "relaying" (’872 Patent, col. 8:3-10).
- Evidence for a Narrower Interpretation: The claim language "relaying data from a first one of the segments to which it is connected to a second one" suggests a specific pass-through or intermediary function. A figure in the patent (Fig. 1) depicts cache nodes as distinct entities on a bus loop, which may support an interpretation that they must do more than just source or sink data to be considered "relaying." ('872 Patent, Fig. 1).
VI. Other Allegations
- Indirect Infringement: The complaint alleges both induced and contributory infringement for the asserted patents. Inducement is based on allegations that Intel provides documentation, datasheets, and software developer's manuals instructing customers on how to use the accused products in an infringing manner (Compl. ¶48-50, ¶75-77). Contributory infringement is based on allegations that the accused processors contain components (e.g., the ring bus system) that are a material part of the invention, are not staple articles of commerce, and are especially adapted for use in an infringing manner (Compl. ¶52-53, ¶79-80).
- Willful Infringement: Willfulness is alleged for all asserted patents. The basis is Defendant's alleged actual knowledge of its infringement, which Plaintiff claims existed at least as of the service of the complaint in a prior lawsuit filed in the District of Delaware (Compl. ¶58, ¶85).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural scope: whether the concept of "programmably interconnecting" from the '763 patent, which is described in the context of highly flexible, reconfigurable processing arrays, can be construed to cover the more structured, ring-based interconnects found in the accused Intel processors.
- A key evidentiary question will be one of functional equivalence: does the accused processors' Last Level Cache perform the specific "relaying" function between distinct bus segments as required by Claim 2 of the '872 patent, or does it operate primarily as a shared data repository for the processor cores, suggesting a potential mismatch in its technical operation?
- A central legal question will concern willfulness and damages: given the allegation that Intel was on notice of these patents from a prior lawsuit, the court will likely focus on whether Intel's conduct rises to the level of objective recklessness required for willful infringement, which could lead to enhanced damages.