DCT

6:19-cv-00498

GlobalFoundries US Inc v. Hisense Group Co Ltd

Log In
Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:19-cv-00498, W.D. Tex., 08/26/2019
  • Venue Allegations: Venue is alleged to be proper for foreign defendants as they are subject to personal jurisdiction in the district. For U.S.-based defendants, venue is based on allegations of maintaining a regular and established place of business in the district (Austin, Texas) and committing acts of infringement therein.
  • Core Dispute: Plaintiff alleges that Defendants’ semiconductor products, manufactured using advanced process nodes, and the downstream electronics incorporating them, infringe patents related to FinFET device structures and semiconductor manufacturing methods.
  • Technical Context: The technology at issue involves foundational techniques for manufacturing modern, high-performance integrated circuits, such as those used in smartphones and other advanced electronics, at process nodes of 28 nanometers and smaller.
  • Key Procedural History: The complaint notes that Plaintiff Globalfoundries acquired a portfolio of 16,000 patents from IBM's microelectronics division in 2015, which included the '418 patent asserted in this action. The complaint itself is alleged to serve as notice to the defendants for the purposes of willfulness and inducement claims.

Case Timeline

Date Event
2006-01-20 ’418 Patent Priority Date
2009-10-09 ’603 Patent Priority Date
2010-07-06 ’418 Patent Issue Date
2013-03-12 ’986 Patent Priority Date
2014-12-16 ’603 Patent Issue Date
2015-01-20 ’986 Patent Issue Date
2015-01-01 Globalfoundries acquires IBM’s patent portfolio (approximate year)
2019-08-26 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,912,603 - "Semiconductor device with stressed fin sections," Issued 12/16/2014

The Invention Explained

  • Problem Addressed: The patent addresses the difficulty of applying traditional performance-enhancing stress techniques to three-dimensional FinFET transistors, as conventional methods like strained over-layers are less effective on the vertical fin sidewalls that form the device channel ('603 Patent, col. 3:1-12).
  • The Patented Solution: The invention proposes creating discontinuous sections of the semiconductor fin by etching gaps in the fin material located between the transistor gate structures. These gaps are then filled with a stress-inducing material (e.g., silicon-germanium), which imparts compressive or tensile stress directly into the adjacent channel regions to improve carrier mobility and device performance ('603 Patent, Abstract; col. 10:46-52). The process uses the gate structures and spacers as a self-aligning mask to precisely locate the stressed regions ('603 Patent, col. 8:13-19).
  • Technical Importance: This method provides a targeted way to integrate beneficial strain into scaled FinFET devices, a key factor for improving transistor speed and efficiency in advanced process nodes ('603 Patent, col. 3:56-66).

Key Claims at a Glance

  • The complaint asserts independent claim 15.
  • Essential elements of claim 15 include:
    • A semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments, wherein each upper surface segment ends at a respective first end sidewall and a respective second end side wall, and wherein each gap is bounded in the first direction by a selected first end sidewall and an adjacent second end sidewall.
    • A stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall.
  • The complaint indicates its allegations are exemplary, reserving the right to assert other claims (Compl. ¶51).

U.S. Patent No. 7,750,418 - "Introduction of metal impurity to change workfunction of conductive electrodes," Issued 07/06/2010

The Invention Explained

  • Problem Addressed: The patent describes a problem in advanced transistors that use high-k dielectrics, where it is difficult to achieve the ideal threshold voltage for turning the transistor on and off. Conventional gate materials used with these new dielectrics result in a non-ideal threshold voltage, particularly for n-type MOSFETs ('418 Patent, col. 1:46-54).
  • The Patented Solution: The invention provides a method to tune the workfunction of the gate stack by introducing specific "workfunction altering metal impurities" into a metal-containing layer (such as titanium nitride, TiN) positioned above the high-k dielectric. By selecting specific impurities (e.g., elements from the Lanthanide series), the workfunction can be shifted to achieve the desired n-type or p-type threshold voltage ('418 Patent, Abstract; col. 2:22-30).
  • Technical Importance: This technology was a key enabler for the industry's transition to high-k/metal gate (HKMG) transistors, providing a crucial method for controlling transistor switching characteristics, which is vital for device performance and power management ('418 Patent, col. 1:55-62).

Key Claims at a Glance

  • The complaint asserts independent claim 27.
  • Essential elements of claim 27 (a method claim) include:
    • Providing a material stack that comprises a dielectric having a dielectric constant of greater than silicon dioxide, a metal-containing material located above said dielectric, and a conductive electrode located directly on an upper surface of said metal-containing material.
    • Introducing at least one workfunction altering metal impurity into said metal-containing material wherein said at least one workfunction altering metal impurity is introduced during forming of a metal impurity containing layer or after formation of a layer containing said metal-containing material.
  • The complaint reserves the right to assert other claims (Compl. ¶51).

Multi-Patent Capsule: U.S. Patent No. 8,936,986 - "Methods of forming finfet devices with a shared gate structure," Issued 01/20/2015

  • Technology Synopsis: The patent discloses a method for simplifying the fabrication of CMOS FinFET devices where N-type and P-type transistors share a common gate structure ('986 Patent, Background). The invention seeks to solve problems associated with complex, multi-step etching processes for forming spacers by proposing a method where a single sidewall spacer is formed around the entire perimeter of the shared sacrificial gate in a "single deposition process operation and a single etching process operation," thereby reducing process complexity and the risk of error ('986 Patent, Abstract; Claim 1).
  • Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶88, 90).
  • Accused Features: The complaint alleges that TSMC’s 16 Nanometer technology infringes by using a method that forms a shared sacrificial gate structure over both N-type and P-type fins and then forms a sidewall spacer around the gate's perimeter in a single deposition and etch process (Compl. ¶88, 92-93).

III. The Accused Instrumentality

Product Identification

  • The complaint identifies a multi-level chain of accused instrumentalities:
    1. Semiconductor Wafers and Dies: Integrated circuits manufactured by Defendant TSMC using its 28nm, 22nm, 20nm, 16/12nm, 10nm, and 7nm process technologies (the "’603, ’418, and ’986 Accused Products") (Compl. ¶4, fn. 1; ¶54, 70, 88).
    2. System-on-Chip (SoC) Devices: SoCs, such as MediaTek’s Helio P22, that are designed by Defendant MediaTek and fabricated by TSMC using the allegedly infringing processes (Compl. ¶41, 63, 80).
    3. Downstream Consumer Products: Electronics, such as smartphones and televisions (e.g., Hisense Infinity F24, BLU VIVO XL4), that incorporate the accused SoCs (Compl. ¶24, 66, 83).

Functionality and Market Context

  • The accused products form the technological foundation of a vast range of modern electronic devices. The complaint positions the defendants as part of an international supply chain, with TSMC acting as the foundry, MediaTek as a fabless chip designer, and Hisense as a downstream original equipment manufacturer (OEM) (Compl. ¶41-42). The complaint alleges that this supply chain leverages Plaintiff's U.S.-developed patented technology to produce chips that "have flooded the U.S. market," directly harming Plaintiff's U.S. investments and manufacturing operations (Compl. ¶47).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

8,912,603 Infringement Allegations

Claim Element (from Independent Claim 15) Alleged Infringing Functionality Complaint Citation Patent Citation
a semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments... The accused integrated circuits, fabricated using TSMC's 16 Nanometer process, allegedly include fins with an upper surface that is interrupted by gaps, creating discontinuous segments. ¶58 col. 8:10-29
a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall. The accused circuits allegedly use a silicon-germanium (SiGe) epitaxial layer as part of an "embedded strain technology" that fills the gaps to induce stress. ¶59 col. 8:30-40
  • Identified Points of Contention:
    • Technical Question: A central factual question is whether TSMC's 16nm process actually involves the specific step of etching gaps into a continuous fin and subsequently refilling them with a stressor material like SiGe. The complaint's allegation of a "SiGe epitaxial layer for embedded strain technology" (Compl. ¶59) will require significant technical evidence, likely from discovery into TSMC's proprietary process flow, to substantiate against the claim's structural requirements.
    • Scope Question: The litigation may explore the scope of "discontinuous upper surface segments." Does this require the fin to be completely severed down to the underlying insulator, as depicted in the patent's embodiments (e.g., '603 Patent, FIG. 16), or could it read on a process that creates shallower trenches that do not fully separate the fin?

7,750,418 Infringement Allegations

Claim Element (from Independent Claim 27) - Alleged Infringing Functionality - Complaint Citation Patent Citation
providing a material stack that comprises a dielectric having a dielectric constant of greater than silicon dioxide, a metal-containing material located above said dielectric, and a conductive electrode located directly on an upper surface of said metal-containing material; TSMC's manufacturing process for p-type FETs is alleged to create a material stack comprising HfO (a high-k dielectric), interfacial TiN (the metal-containing material), and TiN WF (the conductive electrode). - ¶74 col. 7:41-49
and introducing at least one workfunction altering metal impurity into said metal-containing material wherein said at least one workfunction altering metal impurity is introduced... after formation of a layer containing said metal-containing material. The accused process allegedly introduces a "TiAlCOClf fill," identified as the workfunction altering metal impurity, into the metal-containing material after the layer containing that material has already been formed. ¶75 col. 7:60-65
  • Identified Points of Contention:
    • Technical Question: A key issue will be the characterization of the "TiAlCOClf fill" (Compl. ¶75). The analysis will focus on whether this material constitutes a "workfunction altering metal impurity" in the manner described by the patent, which teaches the introduction of specific elements to tune the gate's electrical properties.
    • Scope Question: The infringement analysis will likely turn on whether the term "workfunction altering metal impurity" is limited to the specific elemental classes disclosed in the '418 patent's specification (e.g., Lanthanides, Pd, Pt) or can be interpreted more broadly to cover the complex material compound allegedly used by TSMC ('418 Patent, col. 6:30-56).

V. Key Claim Terms for Construction

Term from the '603 Patent: "discontinuous upper surface segments"

  • Context and Importance: This term is structurally central to claim 15. The infringement determination depends on whether the accused FinFETs contain fins that are physically segmented by gaps, as opposed to being continuous structures. Practitioners may focus on this term because the patent's specification and figures appear to show a specific method of achieving this discontinuity.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue that the plain meaning of "discontinuous" simply requires a break or interruption, and that the claim language itself does not limit the depth or nature of the "gaps" that create this state.
    • Evidence for a Narrower Interpretation: The specification states that "complete removal results in the plurality of discontinuous semiconductor fin sections" ('603 Patent, col. 8:25-29) and the corresponding Figure 16 shows gap 164 extending fully to the underlying insulating layer. A party could argue this embodiment limits the term to require a full-depth severing of the fin.

Term from the '418 Patent: "workfunction altering metal impurity"

  • Context and Importance: This term is critical because infringement of claim 27 hinges on whether the "TiAlCOClf fill" allegedly used by TSMC (Compl. ¶75) falls within its scope. The construction will determine whether the accused process meets this key limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent defines the term functionally as an impurity used "to alter the workfunction of the gate stack" ('418 Patent, col. 6:25-30). This could support an argument that any metallic substance introduced for this purpose is covered, regardless of whether it is explicitly listed.
    • Evidence for a Narrower Interpretation: The specification provides enumerated, specific examples of suitable metal impurities for achieving n-type and p-type workfunction shifts (e.g., "Sc, Y, La, Zr, Hf, V, Nb, Ta, Ti and elements from the Lanthanide Series" for n-type; "Re, Fe, Ru, Co, Rh, Ir, Ni, Pd, and Pt" for p-type) ('418 Patent, col. 6:30-56). A party may argue that these explicit examples limit the scope of the term to the disclosed classes of elemental metals.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement against all defendant groups. The allegations state that TSMC encourages its customers to import and use the infringing chips through sales support, technical symposiums in the U.S., and knowledge of the U.S. as a primary market (Compl. ¶60, 77, 95). MediaTek is alleged to induce its customers by providing technical specifications, data sheets, and marketing materials that promote the use of its SoCs in end products sold in the U.S. (Compl. ¶64, 81, 99). Hisense is alleged to induce infringement by encouraging distributors to import and sell end products containing the accused components (Compl. ¶84).
  • Willful Infringement: Willfulness is alleged against TSMC. The basis for this claim is knowledge of the patents and the alleged infringement obtained "by at least August 26, 2019," the filing date of the complaint. The complaint alleges that any continued infringing activity after this date is willful (Compl. ¶61-62, 78-79, 96-97).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of process verification: does the physical evidence obtained from reverse engineering and discovery confirm that TSMC's accused manufacturing processes include the specific, granular steps required by the patent claims, such as etching and refilling fin gaps ('603 patent) or introducing specific classes of impurities after layer formation ('418 patent)?
  • The case will likely involve a critical question of definitional scope: can the term "workfunction altering metal impurity," which the ’418 patent supports with examples of specific elemental metals, be construed to cover the complex material compound allegedly used in TSMC's process, or is there a fundamental mismatch between the accused material and the patented invention?
  • A key legal battle may concern supply chain liability: what evidence demonstrates that each defendant—the foundry (TSMC), the chip designer (MediaTek), and the downstream OEM (Hisense)—possessed the specific knowledge and affirmative intent to encourage the infringing acts of others in the chain, as required to prove induced infringement for these highly complex and partitioned activities?