GlobalFoundries US Inc v. Guangdong Oujia Holding Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Globalfoundries U.S. Inc. (Delaware)
  • Defendant: Taiwan Semiconductor Manufacturing Company Ltd. (Taiwan); TSMC North America (California); TSMC Technology, Inc. (Delaware); Qualcomm Inc. (Delaware); Qualcomm Technologies, Inc. (Delaware); and multiple OnePlus entities (China)
  • Plaintiff’s Counsel: The Mort Law Firm, PLLC
• Case Identification: 6:19-cv-00499, W.D. Tex., 08/26/2019
• Venue Allegations: Venue for the domestic defendants is alleged based on their having a regular and established place of business within the district (Austin, Texas) and having committed acts of infringement there. For the foreign defendants, venue is alleged to be proper in any district where they are subject to personal jurisdiction.
• Core Dispute: Plaintiff alleges that Defendants' integrated circuits manufactured using advanced FinFET processes, and the consumer electronics containing them, infringe a patent related to methods of creating stress in semiconductor fin structures to improve performance.
• Technical Context: The technology at issue involves FinFET (Fin Field-Effect Transistor) semiconductor architecture, which is fundamental to the manufacturing of modern, high-performance, and power-efficient microprocessors.
• Key Procedural History: The complaint notes that Plaintiff Globalfoundries acquired IBM's microelectronics facilities and its patent portfolio in 2015, which provides context for its ownership of the patent-in-suit. The complaint establishes a basis for willful infringement based on knowledge of the patent as of the complaint's filing date.

Case Timeline

Date	Event
2009-10-09	U.S. Patent No. 8,912,603 Priority Date
2014-12-16	U.S. Patent No. 8,912,603 Issue Date
2019-08-26	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,912,603 - "Semiconductor device with stressed fin sections"

• Patent Identification: U.S. Patent No. 8,912,603, issued December 16, 2014 (’603 Patent). (Compl. ¶48).

The Invention Explained

• Problem Addressed: The patent’s background section describes the difficulty of applying performance-enhancing mechanical stress to FinFET transistors, a modern 3D transistor design. It notes that conventional techniques used for older, planar transistors—such as depositing strained over-layers—are less effective on FinFETs because the transistor channel is primarily on the vertical sidewalls of the fin, not the top surface. (’603 Patent, col. 3:1-11).
• The Patented Solution: The invention proposes creating a semiconductor device by first forming a continuous fin structure, forming gate structures across it, and then selectively etching away sections of the fin in the areas between the gates. These newly created gaps are then filled with a "stress/strain inducing material" (e.g., silicon germanium) that physically pushes or pulls on the remaining fin sections under the gates. This applied force strains the transistor channel, thereby enhancing carrier mobility and device performance. (’603 Patent, Abstract; col. 8:7-50).
• Technical Importance: This method provides a way to introduce localized, targeted stress into the channel of a FinFET, which is a critical technique for improving transistor speed and efficiency as device dimensions continue to shrink. (’603 Patent, col. 3:55-59).

Key Claims at a Glance

• The complaint asserts one or more claims, "including at least claim 15" (Compl. ¶52).
• Independent Claim 15 is a device claim with the following essential elements:
  • A semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments,
  • wherein each upper surface segment ends at a respective first end sidewall and a respective second end side wall,
  • and wherein each gap is bounded in the first direction by a selected first end sidewall and an adjacent second end sidewall;
  • and a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall. (’603 Patent, col. 11:47-col. 12:2).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are integrated circuits fabricated using TSMC's "28 nanometer and smaller technology," with a specific focus on its "7 Nanometer technology" (Compl. ¶18, fn. 1; Compl. ¶52). The complaint names specific System-on-Chips (SoCs) like "Qualcomm's Snapdragon 855 SoCs" and end-user products containing them, such as the "OnePlus 7 Pro" smartphone, as the "Accused Products" (Compl. ¶¶61, 64).

Functionality and Market Context

The complaint alleges that the accused chips are manufactured using a process that creates the infringing device structure (Compl. ¶55). Specifically, it alleges that TSMC’s 7nm process utilizes "a SiGe epitaxial layer for embedded strain technology" to fill gaps between fin sections, which induces the beneficial stress (Compl. ¶57). These high-performance processors are described as being central to the functionality of modern electronic devices and are sold and imported into the United States (Compl. ¶¶61, 65).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

Claim Chart Summary

’603 Patent Infringement Allegations

Claim Element (from Independent Claim 15)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a semiconductor fin extending along a first direction and having an upper surface interrupted by gaps to form discontinuous upper surface segments...	The Accused Products have semiconductor fins that extend in a first direction and include an upper surface interrupted by gaps, resulting in discontinuous upper surface segments.	¶56	col. 8:7-32
wherein each upper surface segment ends at a respective first end sidewall and a respective second end side wall, and wherein each gap is bounded in the first direction by a selected first end sidewall and an adjacent second end sidewall	The complaint alleges that the discontinuous upper surface segments in the Accused Products end at respective first and second end sidewalls, and that the gaps are bounded by these sidewalls.	¶56	col. 10:5-10
a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall	The Accused Products allegedly use a "SiGe epitaxial layer for embedded strain technology" as the stress/strain inducing material, which fills the gaps and is in contact with the sidewalls of the fin segments.	¶57	col. 8:36-50

Identified Points of Contention

• Scope Questions: A central question may be whether the term "gaps," as claimed, is limited to spaces created by etching a previously contiguous fin, as described in the patent's specification (’603 Patent, col. 8:7-10). The infringement analysis may turn on whether TSMC's manufacturing process creates the final accused structure through a method that is structurally and sequentially different from the one described in the patent.
• Technical Questions: The complaint alleges, on "information and belief," that the accused 7nm process results in the claimed structure (Compl. ¶¶52, 56). A key technical question for the court will be what evidence, such as from semiconductor reverse engineering, can be produced to demonstrate that the physical geometry of TSMC's chips precisely matches the "discontinuous upper surface segments" and "gaps" limitations as recited in Claim 15.

V. Key Claim Terms for Construction

• The Term: "gaps"

• Context and Importance: The creation and filling of "gaps" is the central mechanism of the invention for introducing stress. The definition of this term is critical because it will determine whether any space between fin sections in an accused device qualifies, or if the space must have been formed in a particular way (i.e., by etching a continuous fin).

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party arguing for a broader construction may point to the language of Claim 15 itself, which is a device claim describing a final structure ("a semiconductor fin... interrupted by gaps"). This party could argue that the claim is not limited by the process steps described in the specification for forming those gaps.
  • Evidence for a Narrower Interpretation: A party seeking a narrower construction may highlight the patent's consistent description of a specific manufacturing sequence where the gaps are actively created by "selectively etching the fin arrangement 100" to "form[] semiconductor fin sections" (’603 Patent, col. 8:7-10). This may support an argument that "gaps" must be understood as voids created by removing material from a previously continuous structure.

• The Term: "discontinuous upper surface segments"

• Context and Importance: This term describes the resulting state of the fin after the "gaps" are formed. Its construction is important to determine if the fin sections must have originated from a single, unified structure that was later broken apart.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: Proponents of a broader view could argue that the term simply describes a final physical arrangement, and any device containing fin segments that are physically separate ("discontinuous") would meet this limitation, regardless of whether they were ever connected.
  • Evidence for a Narrower Interpretation: The specification describes a process that begins with a "fin arrangement 100" and results in "discontinuous semiconductor fin sections 162" after an etching step (’603 Patent, FIG. 14, col. 8:17-21). This narrative could be used to argue that the "segments" must be understood as remnants of a formerly continuous fin, thereby narrowing the claim's scope.

VI. Other Allegations

• Indirect Infringement: The complaint alleges that TSMC induces infringement by providing customers with the accused chips and offering sales support, technical documentation, and training that encourages their importation and use (Compl. ¶58). It makes similar allegations against Qualcomm for promoting its Snapdragon SoCs via marketing materials, data sheets, and technical specifications (Compl. ¶62).
• Willful Infringement: The complaint alleges willful infringement against the defendants based on their having knowledge of the ’603 patent and their infringing activities "since at least August 26, 2019," the date the complaint was filed and a letter was sent (Compl. ¶¶59, 63). The allegation rests on continued infringement after receiving notice.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of claim scope versus manufacturing process: Can the asserted device claims be interpreted broadly enough to read on the final structure of TSMC's 7nm FinFETs, or will the claims be limited by the specific manufacturing process described in the specification, in which "gaps" are etched into a previously continuous fin?
• A key evidentiary question will be one of structural proof: What will physical analysis of the accused Qualcomm and TSMC chips reveal? The outcome will likely depend on whether the plaintiff can produce definitive evidence that the nanometer-scale geometry of the accused devices maps precisely onto the patent's claims of "discontinuous... segments" separated by stress-material-filled "gaps."