DCT
6:19-cv-00500
GlobalFoundries US Inc v. Avnet Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Globalfoundries U.S. Inc. (Delaware)
- Defendant: Avnet, Inc. (New York)
- Plaintiff’s Counsel: The Mort Law Firm, PLLC
- Case Identification: 6:19-cv-00500, W.D. Tex., 08/26/2019
- Venue Allegations: Plaintiff alleges venue is proper because Defendant Avnet maintains a regular and established place of business within the district and has committed acts of infringement in the district.
- Core Dispute: Plaintiff alleges that Defendant’s importation and sale of certain semiconductor products, manufactured by Taiwan Semiconductor Manufacturing Corporation (TSMC), infringes patents related to advanced semiconductor device structures and manufacturing methods.
- Technical Context: The technology at issue involves foundational techniques for fabricating modern high-performance integrated circuits, including FinFET (Fin Field-Effect Transistor) structures and high-k metal gate (HKMG) technology.
- Key Procedural History: The complaint notes that Plaintiff Globalfoundries acquired the '418 patent as part of a portfolio of 16,000 patents from IBM in 2015, framing its position as a long-term U.S.-based innovator in semiconductor manufacturing in competition with foreign-based foundry TSMC.
Case Timeline
| Date | Event |
|---|---|
| 2006-01-20 | ’418 Patent Priority Date |
| 2009-10-09 | ’603 Patent Priority Date |
| 2010-07-06 | ’418 Patent Issue Date |
| 2013-03-12 | ’986 Patent Priority Date |
| 2014-12-16 | ’603 Patent Issue Date |
| 2015-01-20 | ’986 Patent Issue Date |
| 2019-08-26 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,912,603 - "Semiconductor device with stressed fin sections"
The Invention Explained
- Problem Addressed: The patent describes the difficulty of applying traditional performance-enhancing strain techniques to three-dimensional FinFET transistors. As FinFETs scale to smaller sizes, there is less available space between device gates to incorporate the stress-inducing materials needed to improve carrier mobility and device speed (’603 Patent, col. 3:1-41).
- The Patented Solution: The invention proposes a method to create more room for these stressor materials. It involves selectively etching away portions of the semiconductor fin that lie between the transistor gates, creating well-defined gaps. These gaps are then filled with a stress/strain inducing material (e.g., silicon germanium). This technique allows for a larger volume of stressor material to be placed in close proximity to the device channel, thereby more effectively straining the channel and improving transistor performance (’603 Patent, Abstract; col. 3:56-65).
- Technical Importance: This approach provides a scalable method for integrating beneficial strain into advanced FinFET architectures, a critical factor for continuing performance improvements in leading-edge semiconductor nodes (’603 Patent, col. 3:42-55).
Key Claims at a Glance
- The complaint asserts independent claim 15 (Compl. ¶18, 20).
- The essential elements of claim 15 are:
- A semiconductor fin extending in a first direction with an upper surface interrupted by gaps, forming discontinuous upper surface segments.
- Each gap is bounded by the end sidewalls of adjacent segments.
- A stress/strain inducing material at least partially fills the gaps and is in contact with the end sidewalls.
- The complaint reserves the right to assert other claims (Compl. ¶18).
U.S. Patent No. 7,750,418 - "Introduction of metal impurity to change workfunction of conductive electrodes"
The Invention Explained
- Problem Addressed: The patent notes that when using new high-k dielectric materials in transistor gates (a key innovation for reducing power leakage), it is difficult to achieve the ideal threshold voltage required for proper transistor operation, particularly for n-type MOSFETs (’418 Patent, col. 1:48-55).
- The Patented Solution: The invention describes a method for tuning the workfunction of a gate stack to achieve the desired threshold voltage. This is accomplished by introducing specific "workfunction altering metal impurities" into a metal-containing layer (such as titanium nitride) situated within the gate stack. The specific impurity is chosen to shift the workfunction appropriately for either n-type or p-type transistors, providing precise control over device characteristics (’418 Patent, Abstract; col. 2:40-55).
- Technical Importance: This technique enables the successful integration of high-k metal gate (HKMG) technology, a cornerstone of modern semiconductor manufacturing that allows for the creation of smaller, faster, and more power-efficient transistors (’418 Patent, col. 1:56-62).
Key Claims at a Glance
- The complaint asserts independent method claim 27 (Compl. ¶27, 29).
- The essential steps of claim 27 are:
- Providing a material stack that includes a high-k dielectric, a metal-containing material above the dielectric, and a conductive electrode on top of the metal-containing material.
- Introducing at least one workfunction-altering metal impurity into the metal-containing material, either during or after the formation of that material layer.
- The complaint reserves the right to assert other claims (Compl. ¶27).
U.S. Patent No. 8,936,986 - "Methods of forming finfet devices with a shared gate structure"
Technology Synopsis
This patent addresses manufacturing challenges when creating opposite-type FinFETs (NMOS and PMOS) that share a common gate, a typical configuration in SRAM cells. The invention discloses a more efficient manufacturing method where a sidewall spacer is formed around the entire perimeter of the shared sacrificial gate structure in a single deposition and etch operation, aiming to simplify the process flow and reduce potential for error (’986 Patent, Abstract; col. 1:53-col. 2:24).
Asserted Claims
The complaint asserts at least independent method claim 1 (Compl. ¶37, 39).
Accused Features
The complaint alleges that TSMC’s 16 Nanometer process infringes by forming a shared sacrificial gate over both N-type and P-type fins and then forming a sidewall spacer around the gate's entire perimeter using a single deposition and etch process (Compl. ¶41-42).
III. The Accused Instrumentality
Product Identification
The complaint identifies the accused instrumentalities as integrated circuits manufactured by TSMC using its 28nm, 16nm, and other advanced process nodes. Specific product families named include Xilinx FPGAs (Field Programmable Gate Arrays), ACAPs (Adaptive Compute Acceleration Platforms), and SoCs (Systems on a Chip), such as the Xilinx XCKU3P and XCKU15P families (Compl. ¶5, 18, 27). Defendant Avnet is accused of infringing by importing, selling, and distributing these products (Compl. ¶11).
Functionality and Market Context
The accused products are described as high-performance, advanced semiconductor devices. The complaint positions the manufacturer, TSMC, as a direct competitor to Plaintiff Globalfoundries. It alleges that Avnet’s distribution of these TSMC-fabricated products in the U.S. harms Globalfoundries’ investments in U.S.-based manufacturing (Compl. ¶11, 19). The infringement allegations specifically tie TSMC's 16nm process to the '603 and '986 patents, and TSMC's 28nm and 16nm processes to the '418 patent (Compl. ¶18, 22, 27, 31, 37, 40). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’603 Patent Infringement Allegations
| Claim Element (from Independent Claim 15) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor device | The accused products are semiconductor devices, specifically integrated circuits. | ¶21 | col. 2:1-2 |
| a semiconductor fin extending along a first direction and have an upper surface interrupted by gaps to form discontinuous upper surface segments... | The accused products are fabricated with TSMC's 16nm process, which allegedly creates fins with an upper surface interrupted by gaps to form discontinuous segments. | ¶22 | col. 10:1-12 |
| a stress/strain inducing material at least partially filling the gaps and in contact with each second end sidewall and each first end sidewall. | The accused products allegedly use a SiGe epitaxial layer for embedded strain technology, which serves as the stress/strain inducing material that fills the gaps. | ¶23 | col. 10:19-25 |
- Identified Points of Contention: The core of the dispute for the '603 Patent will likely be factual and technical. A primary question for the court will be whether reverse engineering of TSMC's 16nm products confirms the presence of the claimed structure. The analysis will focus on whether the semiconductor fins are physically "interrupted by gaps" and whether the SiGe material "fill[s] the gaps" in the specific manner required by the claim.
’418 Patent Infringement Allegations
| Claim Element (from Independent Claim 27) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a method of changing workfunction of a conductive stack comprising: | The complaint alleges that TSMC's manufacturing process is a method of changing the workfunction of conductive stacks in its devices. | ¶30 | col. 2:40-41 |
| providing a material stack that comprises a dielectric having a dielectric constant of greater than silicon dioxide, a metal-containing material located above said dielectric, and a conductive electrode located directly on an upper surface of said metal-containing material; | TSMC's process allegedly creates a stack comprising HfO (high-k dielectric), TiN (metal-containing material), and TiN WF (conductive electrode). | ¶31 | col. 2:25-29 |
| and introducing at least one workfunction altering metal impurity into said metal-containing material... after formation of a layer containing said metal-containing material. | TSMC's process allegedly introduces a "TiAlCOCIF fill" as the impurity into the TiN layer after the TiN layer has already been formed. | ¶32 | col. 2:50-55 |
- Identified Points of Contention: Since the '418 Patent claims a method practiced abroad by TSMC, the suit against the distributor Avnet relies on 35 U.S.C. § 271(g). A key legal question will be whether the accused Xilinx chips are "materially changed by subsequent processes" or become "trivial and nonessential components of another product," which are statutory defenses to a § 271(g) claim (Compl. ¶33). A technical question will be whether the alleged "TiAlCOCIF fill" constitutes a "workfunction altering metal impurity" and whether it is "introduced into" the TiN layer as the claim requires, which may become a point of claim construction.
V. Key Claim Terms for Construction
For the '603 Patent
- The Term: "gaps"
- Context and Importance: The claim requires the fin's "upper surface" to be "interrupted by gaps." The physical characteristics of these "gaps" in the accused products compared to the patent's teachings will be central to the infringement analysis. Practitioners may focus on this term because its scope will determine whether any recess or etching between gates meets the limitation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the gaps as being formed by "selectively etching the fin arrangement" (’603 Patent, col. 2:49-53). This could support an interpretation that any etched recess between the gate structures qualifies as a "gap."
- Evidence for a Narrower Interpretation: The figures and corresponding description illustrate "discontinuous semiconductor fin sections" separated by a "gap 164," which appears to be a complete removal of the fin material down to the underlying insulating layer (’603 Patent, FIG. 15; col. 8:26-30). This may support a narrower construction requiring a full separation between fin segments.
For the '418 Patent
- The Term: "introducing... into said metal-containing material"
- Context and Importance: This phrase is critical for determining whether TSMC's alleged manufacturing step meets the claim limitation. The dispute will likely center on the physical meaning of "introducing into"—whether layering is sufficient, or if diffusion or intermixing is required.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes introducing the impurity "during forming of a metal impurity containing layer or after formation" (’418 Patent, claim 27). The "after formation" language, combined with descriptions of layering followed by a thermal anneal, could support a reading where depositing an impurity layer on top of the metal-containing material constitutes "introducing into" (’418 Patent, col. 7:56-63).
- Evidence for a Narrower Interpretation: The specification describes embodiments where the impurity is "continuously distributed throughout the entire thickness" or in "discrete regions within" the material layer (’418 Patent, col. 6:1-4). This language could be used to argue for a narrower definition that requires more than mere surface contact, suggesting some degree of physical integration or diffusion.
VI. Other Allegations
- Indirect Infringement: The complaint focuses primarily on direct infringement by Avnet through its importation, use, and sale of the accused products (Compl. ¶19, 28, 38). For the method claims ('418 and '986 patents), the action is based on 35 U.S.C. § 271(g), which treats the importation of a product made by a patented process as direct infringement. The complaint also makes general allegations of inducement based on Avnet's "demonstrations, evaluations, and testing" and "training courses," suggesting Avnet encourages its customers to use the products in an infringing manner (Compl. ¶19, 28).
- Willful Infringement: The complaint does not plead specific facts to support a claim for willful infringement, such as alleging that Avnet had pre-suit knowledge of the patents. It does include a prayer for attorneys' fees on the basis that the case is "exceptional" pursuant to 35 U.S.C. § 285 (Compl. p. 17).
VII. Analyst’s Conclusion: Key Questions for the Case
- A question of process versus product: The case will fundamentally depend on a factual comparison between TSMC's proprietary manufacturing processes and the structures described in Globalfoundries' patents. The outcome will likely be determined by extensive discovery, reverse engineering of the accused chips, and competing expert testimony on the nature of nanometer-scale semiconductor fabrication.
- A question of importation liability: For the '418 and '986 method patents, a central legal issue will be the application of 35 U.S.C. § 271(g). The court will have to consider whether the imported Xilinx chips are "made by" the patented processes and, if so, whether they are "materially changed" by subsequent manufacturing steps before their importation, a statutory defense that could shield the distributor, Avnet, from liability.
- A question of definitional scope: The resolution of the case may turn on the construction of key claim terms. A core issue will be whether the term "gaps" in the '603 patent can be construed to read on the structures in TSMC's devices, and whether the act of "introducing... into" a material in the '418 patent covers TSMC's alleged manufacturing technique. The court's interpretation of these terms could be dispositive.