ParkerVision, Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: ParkerVision, Inc. (Florida)
  • Defendant: Intel Corporation (Delaware)
  • Plaintiff’s Counsel: The Mort Law Firm, PLLC
• Case Identification: 6:20-cv-00562, W.D. Tex., 05/28/2021
• Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Intel is registered to do business in Texas, maintains regular and established places of business in the district, including its "Austin Offices," and has committed acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant’s radio frequency (RF) transceiver integrated circuits, used in cellular devices, infringe three patents related to RF signal down-conversion and up-conversion technologies.
• Technical Context: The technology at issue involves methods for converting RF signals between high frequencies used for wireless transmission and lower frequencies used for baseband processing, a fundamental function in modern communications electronics.
• Key Procedural History: The complaint does not allege any prior litigation between the parties or any administrative patent challenges.

Case Timeline

Date	Event
1997-10-21	Patent Priority Date ('706, '508, '108 Patents)
2000-04-11	U.S. Patent No. 6,049,706 Issued
2006-05-23	U.S. Patent No. 7,050,508 Issued
2012-05-29	U.S. Patent No. 8,190,108 Issued
2016-09-15	Apple iPhone 7/7 Plus (containing PMB5750) teardown published
2017-02-07	Intel publishes paper allegedly describing PMB5750 chip
2017-11-08	Apple iPhone 8/8+/X (containing PMB5757) teardown published
2018-09-21	Apple iPhone XS/XS Max (containing PMB5762) teardown published
2021-05-28	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,049,706 - "Integrated Frequency Translation and Selectivity", Issued April 11, 2000

The Invention Explained

• Problem Addressed: The patent describes a problem in conventional radio receivers where a wide-band "band-select" filter is used at the front-end before amplification and frequency mixing (’706 Patent, col. 1:56-62). This wide filter can allow strong, undesired signals to pass through with the desired signal, potentially overloading downstream components like low-noise amplifiers and mixers, causing non-linear operation and the generation of spurious signals that interfere with the desired signal (’706 Patent, col. 2:9-20).
• The Patented Solution: The invention proposes a unified module that performs both frequency down-conversion and filtering in an integrated manner (’706 Patent, col. 3:28-34). It achieves this by under-sampling a high-frequency input signal to create a down-converted image and then combining delayed versions of both this input sample and the module's own output signal to generate a filtered, down-converted output (’706 Patent, col. 3:30-34, Fig. 17). This architecture effectively performs narrowband filtering at the RF input stage, rejecting interfering signals before they can cause distortion in subsequent components.
• Technical Importance: This approach enabled the realization of high-Q filters at high RF frequencies, which was difficult with conventional techniques, thereby improving receiver selectivity and reducing interference in crowded spectrums (’706 Patent, col. 11:47-50).

Key Claims at a Glance

• The complaint asserts at least independent claim 1 (Compl. ¶42).
• Essential elements of claim 1 include:
  • A frequency translator comprising a down-convert and delay module to under-sample an input signal to produce a down-converted image sample and to delay said sample.
  • A filter comprising at least a portion of the down-convert and delay module.
  • The filter further comprises at least one delay module to delay instances of an output signal.
  • The filter further comprises an adder to combine the delayed input sample with at least one delayed instance of the output signal to generate a current instance of the output signal.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,050,508 - "Method and System for Frequency Up-Conversion with a Variety of Transmitter Configurations", Issued May 23, 2006

The Invention Explained

• Problem Addressed: The patent addresses the architecture of RF transmitters. It notes that conventional transmitters for different modulation schemes (FM, PM, AM) often require distinct and complex circuitries, including oscillators, modulators, and multipliers, to up-convert a baseband information signal to a high-frequency signal for transmission (’508 Patent, col. 1:16-19).
• The Patented Solution: The invention discloses a simplified up-conversion system that uses a stable, low-frequency reference signal (’508 Patent, Abstract). A key step is using a switching module to gate a bias signal, controlled by a modulated oscillating signal, to create a harmonically rich waveform, such as a square wave or pulse train (’508 Patent, col. 18:8-14, Fig. 19D). A filter then selects one of the higher-frequency harmonics of this waveform as the final up-converted signal for transmission (’508 Patent, col. 18:15-20). This method allows for up-conversion using simpler components.
• Technical Importance: This technique provides an efficient method for generating high-frequency signals from a low-frequency source, potentially reducing the cost, size, and power consumption of RF transmitters (’508 Patent, col. 16:38-42).

Key Claims at a Glance

• The complaint asserts at least independent claim 3 (Compl. ¶48).
• Essential elements of claim 3 (a means-plus-function claim) include:
  • "pulse shaping means" for shaping a string of pulses from a reference signal.
  • "aperture generation means" coupled to the pulse shaping means for generating a string of multiple pulses.
  • "gating means" for gating a bias signal under the control of the string of multiple pulses to generate a periodic signal with a plurality of harmonics.
• The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule: U.S. Patent No. 8,190,108 - "Method and System for Frequency Up-Conversion", Issued May 29, 2012

• Technology Synopsis: The ’108 Patent, like the ’508 Patent, is directed to frequency up-conversion for transmitters. The invention describes a frequency conversion module with a switch (e.g., a transistor) that is configured to up-convert a signal based on a control signal (e.g., from a local oscillator) and a bias signal, with the resulting signal being routed through other switches for transmission by an antenna (’108 Patent, Abstract).
• Asserted Claims: Independent claim 8 (Compl. ¶54).
• Accused Features: The complaint alleges that the Intel Chips include a frequency conversion module with a transistor configured for up-conversion, a pulse shaper (e.g., a digital phase-locked loop), and an oscillating signal generator, which together perform the claimed up-conversion function (Compl. ¶¶56-57).

III. The Accused Instrumentality

Product Identification

• The accused products are "Intel Chips," which are identified as receiver, transmitter, and/or transceiver integrated circuits (Compl. ¶26). Specific models named are the Intel PMB 5750, PMB 5757, and PMB 5762 (the "PMB Chips") (Compl. ¶26).

Functionality and Market Context

• The complaint alleges these chips provide cellular connectivity for widely-used consumer devices, including Apple's iPhone 7, 7 Plus, 8, 8 Plus, X, XR, XS, and XS Max (Compl. ¶¶27-28). The complaint alleges these chips perform both down-conversion for receiving signals and up-conversion for transmitting them (Compl. ¶¶44, 50, 56). In 2019, Apple acquired Intel's smartphone modem business, which included these products, for $1 billion, suggesting their market significance (Compl. ¶31).

IV. Analysis of Infringement Allegations

'706 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a frequency translator, comprising a down-convert and delay module to under-sample an input signal...to produce an input sample of a down-converted image of said input signal, and to delay said input sample	Each Intel Chip includes a frequency translator, comprising a down-convert and delay module to under-sample a high frequency RF signal to produce an input sample of a down-converted image and to delay said input sample.	¶44	col. 16:15-24
a filter, comprising...at least one delay module to delay instances of an output signal	The filter in each Intel Chip includes at least one delay module to delay instances of an output signal.	¶44	col. 16:35-37
and an adder...to combine at least said delayed input sample with at least one of said delayed instances of said output signal to generate an instance of said output signal	The filter in each Intel Chip includes an adder (e.g., operational amplifier with parallel resistor-capacitor feedback) to combine the delayed input sample with at least one delayed instance of the output signal.	¶44	col. 16:38-44

'508 Patent Infringement Allegations

Claim Element (from Independent Claim 3)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
pulse shaping means for shaping a string of pulses from a reference signal	Each Intel Chip includes a pulse shaping means, identified as logic devices, for shaping a string of pulses from a local oscillator (LO) signal.	¶50	col. 46:45-50
aperture generation means...for generating a string of multiple pulses from said string of pulses	Each Intel Chip includes an aperture generation means, identified as a digital phase locked loop, for generating multiple pulses from the shaped string of pulses.	¶50	col. 47:1-6
gating means...for gating a bias signal under the control of said string of multiple pulses to generate a periodic signal having a plurality of harmonics...	Each Intel Chip includes a gating means, identified as an inverter, for gating a bias signal under the control of the multiple pulses to generate a periodic signal with harmonics. The complaint provides a die micrograph alleged to be of the accused PMB5750 chip, showing functional blocks including a "DPLL" (Digital Phase-Locked Loop) which may relate to the accused "aperture generation means" (Compl. p. 9).	¶50	col. 35:25-33

Identified Points of Contention:

• Scope Questions ('706 Patent): The analysis may turn on the definition of "under-sample." A key question is whether the accused chips' sampling process, which the complaint alleges occurs at a rate below the Nyquist rate (Compl. ¶45), performs the specific function of generating a "down-converted image" in the manner required by the patent specification's teachings on unified down-conversion and filtering.
• Technical Questions (Means-Plus-Function for '508 Patent): A central dispute for the ’508 Patent will be construing the "means-plus-function" claim terms. The court must first identify the corresponding structure described in the patent's specification that performs the recited functions (e.g., "pulse shaping," "aperture generation"). Infringement will then depend on whether the structures identified in the complaint (e.g., "logic devices," "digital phase locked loop") are the same as or structurally equivalent to those disclosed in the patent.

V. Key Claim Terms for Construction

For the '706 Patent:

• The Term: "under-sample"
• Context and Importance: This term is at the heart of the claimed down-conversion method. Its definition will determine whether the accused chips' sampling architecture infringes. The dispute may focus on whether "under-sample" simply means sampling below the Nyquist rate, or if it requires the specific aliasing and filtering architecture disclosed in the patent to create a "down-converted image."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The claims do not appear to further limit the term, and the specification discusses the concept in relation to aliasing, which is a general principle of sampling theory (’706 Patent, col. 18:49-54).
  • Evidence for a Narrower Interpretation: The specification describes the under-sampling in the specific context of a "unified downconverting and filtering (UDF) module" that combines delayed input and output samples (’706 Patent, Fig. 11, col. 16:15-44). A party could argue the term should be limited to sampling performed within such an integrated architecture.

For the '508 Patent:

• The Term: "aperture generation means"
• Context and Importance: As a means-plus-function limitation under 35 U.S.C. § 112(f), the scope of this term is not its plain meaning but is limited to the corresponding structure disclosed in the specification and its equivalents. The complaint alleges this corresponds to a "digital phase locked loop" (DPLL) (Compl. ¶50). Practitioners may focus on whether the structures disclosed in the patent are equivalent to a modern DPLL.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation (supporting Plaintiff's alleged structure): A party might argue that the function of "generating a string of multiple pulses" is performed by any circuit that can create multiple apertures from a single pulse, and that a DPLL is a well-known equivalent structure for achieving such timing control.
  • Evidence for a Narrower Interpretation (limiting the structure): The specification describes specific embodiments for generating multiple pulses, such as using a series of delay elements and logic gates (’508 Patent, Fig. 39A, Fig. 40A). A party could argue the term's scope is limited to these specific circuit topologies and their equivalents, and that a complex, feedback-controlled DPLL is a non-equivalent, later-developed technology.

VI. Other Allegations

• Indirect Infringement: The complaint does not contain specific factual allegations to support claims of induced or contributory infringement. Each count alleges only "direct[] infringe[ment]" (Compl. ¶¶42, 48, 54).
• Willful Infringement: The complaint does not allege that Intel had pre-suit knowledge of the patents-in-suit or that its alleged infringement has been willful. The prayer for relief includes a request for damages under 35 U.S.C. § 284, which allows for enhancement in cases of willful infringement, but the factual predicate for willfulness is not pled in the body of the complaint.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of claim scope for means-plus-function terms: For the '508 patent, can the structures for "pulse shaping means" and "aperture generation means," as disclosed in the 1997-priority-date patent, be construed to cover the complex "logic devices" and "digital phase locked loop" circuitry alleged to be in Intel’s modern RF transceivers?
2. A second central issue will be one of technical and definitional mapping: For the '706 patent, does the accused products' architecture perform "under-sampling" to create a "down-converted image" that is then combined with delayed output signals, as required by the claim, or is there a fundamental mismatch in the operational principle of the accused down-converter?
3. An evidentiary question will be one of structural proof: What evidence will be presented to demonstrate that the internal operations of the accused Intel Chips, as depicted in materials like the die micrograph (Compl. p. 9), actually perform the specific steps and functions recited in the asserted claims of the three patents-in-suit?