DCT

6:20-cv-00562

ParkerVision, Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-00562, W.D. Tex., 07/16/2020
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant Intel maintains regular and established places of business in Austin, employs over 1,700 individuals in the area, and has committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s radio frequency (RF) transceiver chips, used in popular smartphones, infringe three patents related to frequency down-conversion and up-conversion technologies.
  • Technical Context: The technology at issue involves methods for converting RF signals between higher and lower frequencies, a fundamental process for enabling wireless communication in devices like smartphones by allowing them to receive and transmit signals.
  • Key Procedural History: The complaint does not note any prior litigation between the parties or challenges to the patents-in-suit. However, public records indicate that U.S. Patent No. 8,190,108, one of the patents-in-suit, was subject to a post-filing Inter Partes Review (IPR2021-00346). The proceeding resulted in the cancellation of claims 1, 6-9, 12, and 17-20, which includes Claim 8, the only claim asserted from the ’108 patent in this complaint.

Case Timeline

Date Event
1998-10-21 Earliest Priority Date for ’706, ’508, and ’108 Patents
2000-04-11 U.S. Patent No. 6,049,706 Issues
2006-05-23 U.S. Patent No. 7,050,508 Issues
2012-05-29 U.S. Patent No. 8,190,108 Issues
2016-09-16 Apple iPhone 7 Launch (incorporating accused Intel PMB5750 chip)
2020-07-16 Complaint Filed
2021-01-14 Inter Partes Review (IPR2021-00346) filed against the ’108 Patent
2024-10-21 IPR Certificate issues, cancelling asserted Claim 8 of the ’108 Patent

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,049,706 - Integrated Frequency Translation and Selectivity (Issued Apr. 11, 2000)

The Invention Explained

  • Problem Addressed: The patent describes the problem of conventional RF receivers using wide-band pre-selection filters prior to amplification and frequency mixing. This architecture allows strong, unwanted signals to pass through to components with limited dynamic ranges, which can generate spurious signals and interfere with the reception of the desired, often weaker, signal (’706 Patent, col. 1:50–2:1).
  • The Patented Solution: The invention proposes a unified module that performs frequency down-conversion and filtering as an integrated operation. This is achieved by under-sampling an input signal and then combining delayed samples of the input signal with delayed instances of the generated output signal to construct the final filtered, down-converted output (’706 Patent, Abstract; col. 3:25-40). This architecture allows for highly selective, narrow-band filtering to occur at the RF input stage, rejecting interfering signals before they can cause non-linear distortion.
  • Technical Importance: This integrated approach was aimed at enabling smaller, cheaper, and more power-efficient RF receivers by replacing multiple discrete, and often bulky, analog components with a unified digital-style architecture (Compl. ¶23).

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 1 (Compl. ¶42).
  • The essential elements of independent claim 1 are:
    • A frequency translator, comprising a down-convert and delay module to under-sample an input signal to produce a delayed, down-converted input sample.
    • A filter, comprising at least a portion of the down-convert and delay module, at least one delay module for an output signal, and an adder to combine the delayed input sample with delayed instances of the output signal to generate a new instance of the output signal.

U.S. Patent No. 7,050,508 - Method and System for Frequency Up-Conversion with a Variety of Transmitter Configurations (Issued May 23, 2006)

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of efficiently up-converting a lower-frequency baseband signal to a higher RF frequency for transmission, a core function of a wireless transmitter. The complaint provides context that conventional technologies were large and required significant power (Compl. ¶21).
  • The Patented Solution: The invention describes a method of up-conversion that avoids traditional mixers. It uses a switching element to gate a bias signal (e.g., a DC voltage) under the control of a modulated oscillating signal. This process generates a harmonically rich signal—a signal containing the fundamental frequency plus numerous integer multiples (harmonics). A desired harmonic, which is at a higher frequency, is then filtered to become the final transmitted RF signal (’508 Patent, Abstract; col. 2:25-45).
  • Technical Importance: This up-conversion technique was designed to provide size, cost, and power-saving benefits for RF transmitters, complementing the down-conversion technology for receivers (Compl. ¶24).

Key Claims at a Glance

  • The complaint asserts infringement of at least Claim 3 (Compl. ¶48).
  • The essential elements of independent claim 3, which is a means-plus-function claim, are:
    • "pulse shaping means" for shaping pulses from a reference signal.
    • "aperture generation means" for generating a string of multiple pulses from the shaped pulses.
    • "gating means" for gating a bias signal under the control of the multiple-pulse string to generate a periodic signal containing a plurality of harmonics at a desired frequency.

U.S. Patent No. 8,190,108 - Method and System for Frequency Up-Conversion

  • Patent Identification: U.S. Patent No. 8,190,108, "Method and System for Frequency Up-Conversion," issued May 29, 2012 (Compl. ¶38).
  • Technology Synopsis: The ’108 Patent also discloses technology for frequency up-conversion in RF transmitters. The invention describes a frequency conversion module with switches (e.g., transistors) configured to up-convert a baseband signal based on a control signal and a bias signal for transmission via an antenna ('108 Patent, Abstract; Compl. ¶56).
  • Asserted Claims: The complaint asserts infringement of at least Claim 8 (Compl. ¶54). Notably, Claim 8 was cancelled in the post-filing IPR2021-00346.
  • Accused Features: The complaint alleges that the Intel Chips include a frequency conversion module, pulse shaper, and oscillating signal generator that perform the functions recited in the claims (Compl. ¶¶56-57).

III. The Accused Instrumentality

Product Identification

  • The accused instrumentalities are Intel's RF transceiver chips/modems, specifically identified as the Intel PMB5750, PMB5757, and PMB5762 (collectively, the "Intel Chips") (Compl. ¶26).

Functionality and Market Context

  • The Intel Chips are alleged to provide cellular connectivity for smartphones and were incorporated into several generations of Apple iPhones, including the iPhone 7, 8, X, XR, and XS models (Compl. ¶¶27-29). The complaint alleges that the structure, function, and operation of the PMB5757 and PMB5762 chips are substantially similar to the PMB5750 with respect to the patented features (Compl. ¶30). The complaint includes a die micrograph from a 2017 Intel technical paper, alleging it illustrates the Intel PMB5750 chip and identifies key functional blocks like the DPLL (Digital Phase Locked Loop) (Compl. ¶29, p. 9). This micrograph shows labeled sections of the accused chip, including "DPLL," "TX-H," "TX-L," and "TX-M" (Compl. p. 9). In December 2019, Apple acquired Intel's smartphone modem business (Compl. ¶31).

IV. Analysis of Infringement Allegations

’706 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a frequency translator, comprising a down-convert and delay module to under-sample an input signal ... to produce an input sample of a down-converted image of said input signal, and to delay said input sample Each Intel Chip includes a down-convert and delay module that under-samples a high frequency RF signal to produce a delayed sample of a down-converted image. ¶44 col. 15:44-16:4
a filter, comprising at least a portion of said down-convert and delay module, at least one delay module to delay instances of an output signal, and an adder...to combine at least said delayed input sample with at least one of said delayed instances of said output signal to generate an instance of said output signal Each Intel Chip also includes a filter comprising part of the down-convert and delay module, at least one delay module for the output signal, and an adder (e.g., an operational amplifier) to combine the delayed signals. ¶44 col. 16:30-52
  • Identified Points of Contention:
    • Technical Question: The complaint alleges the accused chips under-sample according to a control signal (e.g., a local oscillator) whose frequency is governed by a specific mathematical relationship to the input signal and the down-converted image (Compl. ¶45). A central technical question will be what evidence demonstrates that the accused chips operate according to this precise claimed formula.
    • Scope Question: The complaint provides "operational amplifier with parallel resistor-capacitor feedback" as an example of the claimed "adder" (Compl. ¶44). The litigation may raise the question of whether this specific circuit structure, if found in the accused device, falls within the scope of the term "adder" as it is used and defined within the patent.

’508 Patent Infringement Allegations

Claim Element (from Independent Claim 3) Alleged Infringing Functionality Complaint Citation Patent Citation
pulse shaping means for shaping a string of pulses from a reference signal... Each Intel Chip includes pulse shaping means (e.g., logic devices) for shaping a string of pulses from a local oscillator (LO) signal. ¶50 col. 48:3-23
aperture generation means...for generating a string of multiple pulses from said string of pulses Each Intel Chip includes aperture generation means (e.g., a digital phase locked loop) to generate multiple pulses from the shaped string of pulses. ¶50 col. 49:60-50:20
gating means for gating a bias signal...to generate a periodic signal having a plurality of harmonics at least one of which is at a desired frequency Each Intel Chip includes gating means (e.g., an inverter) for gating a steady bias signal under the control of the pulse string to generate a periodic, harmonically-rich signal. ¶50 col. 35:36-36:50
  • Identified Points of Contention:
    • Scope Question (Means-Plus-Function): As Claim 3 uses means-plus-function language, a key legal dispute will be the proper construction of these terms. For example, does the accused "digital phase locked loop," which is identified on the die micrograph (Compl. p. 9), constitute a structural equivalent to the specific delay-and-logic-gate circuits disclosed in the patent's specification (e.g., Fig. 79) for performing the function of "generating a string of multiple pulses"?
    • Technical Question: The claim requires "gating a bias signal" to generate a periodic signal with multiple harmonics. The complaint identifies an "inverter" as the gating means (Compl. ¶50). A technical question may arise as to whether the accused inverter actually gates a DC bias signal to create a harmonically rich intermediate signal, or if it performs a different up-conversion function not contemplated by the patent.

V. Key Claim Terms for Construction

For the ’706 Patent (Claim 1):

  • The Term: "under-sample"
  • Context and Importance: The invention's core concept of integrated down-conversion and filtering is achieved through a specific method of sampling. The definition of "under-sample" is therefore critical to determining infringement, as it must describe the operation of the accused Intel Chips.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests a functional definition, stating that the effect of repetitive sampling "is to translate the frequency (that is, down-convert) of the input signal to a desired lower frequency" (’706 Patent, col. 15:44-49). This could support a construction covering various methods of sampling that result in frequency translation.
    • Evidence for a Narrower Interpretation: The specification also ties the sampling to a specific mathematical relationship, stating that the sampling is performed "according to a control signal, wherein a frequency of said control signal is equal to a frequency of said input signal plus or minus a frequency of said down-converted image, divided by n" (’706 Patent, Claim 1). This language may support a narrower construction requiring proof of this precise formula.

For the ’508 Patent (Claim 3):

  • The Term: "aperture generation means"
  • Context and Importance: This is a means-plus-function term, so its scope is limited to the structures disclosed in the specification and their equivalents. The infringement analysis will depend on whether the accused "digital phase locked loop" (DPLL) is a structural equivalent to what the patent discloses. Practitioners may focus on this term because the complaint's primary evidence for this element is the labeling of a "DPLL" on a die micrograph (Compl. p. 9).
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation (supporting equivalence): A party could argue that the patent describes the function as "generating a string of multiple pulses from said string of pulses" (’508 Patent, col. 76:2-4). Any structure that performs this function in substantially the same way to achieve the same result, such as a DPLL in a modern transmitter, could be argued to be an equivalent.
    • Evidence for a Narrower Interpretation (opposing equivalence): A party could argue the scope is limited to the specific embodiments shown, such as the circuits in Fig. 79 that use discrete delay elements and logic gates to create multiple pulses (’508 Patent, col. 49:60-50:20). They may argue a DPLL is a well-known, distinct component that is not an equivalent to these disclosed structures.

VI. Other Allegations

The complaint alleges only direct infringement for each of the patents-in-suit and does not include allegations of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Structural Equivalence under § 112(f): For the '508 patent, a central issue will be one of means-plus-function construction. Can the accused "digital phase locked loop," a complex integrated circuit block, be proven to be a structural equivalent to the specific pulse-generation circuits disclosed in the patent's specification, or does it represent a distinct, non-infringing technology?

  2. Operational Matching: For the '706 patent, a key evidentiary question will be one of functional correspondence. What technical evidence can be presented to demonstrate that the accused Intel Chips perform sampling according to the precise mathematical formula recited in Claim 1, which dictates the relationship between the control, input, and down-converted signal frequencies?

  3. Claim Viability: A threshold legal issue for the '108 patent is its justiciability. Given that the sole asserted claim, Claim 8, was cancelled in an Inter Partes Review proceeding subsequent to the filing of the complaint, the court will need to address whether any valid cause of action for infringement of this patent remains.