DCT
6:20-cv-00966
Acqis LLC v. ASUSTeK Computer Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Acqis LLC (Texas)
- Defendant: ASUSTeK Computer, Inc. (Taiwan)
- Plaintiff’s Counsel: Scott, Douglass & McConnico, LLP
- Case Identification: 6:20-cv-00966, W.D. Tex., 10/15/2020
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation that does not reside in the United States and may therefore be sued in any judicial district.
- Core Dispute: Plaintiff alleges that Defendant’s computer products, including laptops, desktops, servers, and motherboards, infringe a portfolio of nine patents related to high-speed serial data transmission technologies for computer interconnects.
- Technical Context: The technology concerns the use of low-voltage differential signaling (LVDS) to replace older, parallel data buses, enabling faster data speeds, lower power consumption, and reduced pin counts in foundational interconnects like PCI Express and USB.
- Key Procedural History: The complaint alleges that Plaintiff provided Defendant with actual notice of infringement via a letter on or around May 15, 2018, which identified the asserted patents and accused product categories. The complaint also notes a prior lawsuit involving related patents that resulted in a significant jury verdict against IBM.
Case Timeline
| Date | Event |
|---|---|
| 1999-05-14 | Earliest Priority Date for ’768, ’750, ’359, ’977, ’797, ’140, ’654 Patents |
| 2005-02-10 | Earliest Priority Date for ’739 Patent |
| 2005-03-31 | Earliest Priority Date for ’769 Patent |
| 2013-12-17 | U.S. Patent No. RE44,654 Issued |
| 2014-01-07 | U.S. Patent No. 8,626,977 Issued |
| 2014-01-28 | U.S. Patent No. RE44,739 Issued |
| 2014-06-17 | U.S. Patent No. 8,756,359 Issued |
| 2014-09-16 | U.S. Patent No. RE45,140 Issued |
| 2015-03-10 | U.S. Patent No. 8,977,797 Issued |
| 2016-12-27 | U.S. Patent No. 9,529,768 Issued |
| 2016-12-27 | U.S. Patent No. 9,529,769 Issued |
| 2017-07-11 | U.S. Patent No. 9,703,750 Issued |
| 2018-05-15 | ACQIS allegedly provides ASUS with actual notice of infringement |
| 2020-10-15 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions" (Issued Dec. 27, 2016)
The Invention Explained
- Problem Addressed: The patent’s background section describes the limitations of traditional computer interfaces, such as the Peripheral Component Interconnect (PCI) bus, which used a large number of parallel signal channels. This approach was not "cable friendly," consumed significant power, generated electrical noise, and was difficult to scale for higher speeds ('977 Patent, col. 3:9-52, incorporated by reference).
- The Patented Solution: The invention proposes replacing the parallel PCI bus with a high-speed serial interface that uses Low Voltage Differential Signaling (LVDS). This interface employs pairs of unidirectional channels to transmit data in opposite directions, dramatically reducing the number of required pins and conductive lines while enabling higher data rates and lower power consumption ('977 Patent, col. 4:1-10, Fig. 6).
- Technical Importance: This shift from parallel to high-speed serial communication was a foundational development for modern computer architectures, enabling standards like PCI Express and high-speed USB that are essential for current computing performance (Compl. ¶¶ 1, 31-33).
Key Claims at a Glance
- The complaint asserts independent claims 10 and 33.
- Claim 10 (Printed Circuit Board):
- A printed circuit board
- A central processing unit (CPU)
- A peripheral bridge directly coupled to the CPU without an intervening PCI bus
- An LVDS channel directly extending from the peripheral bridge, comprising two unidirectional, serial channels of multiple differential signal line pairs to convey data in opposite directions
- Wherein the LVDS channel conveys address and data bits of a PCI bus transaction in serial form
- Claim 33 (Computer):
- A computer comprising a CPU with an integrated interface controller
- Directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs
- To transmit encoded address and data bits of a PCI bus transaction in opposite directions
- System memory directly coupled to the CPU
- A mass storage hard drive coupled to the CPU
- Other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially in opposite directions
- The complaint reserves the right to assert additional claims (Compl. ¶¶ 137, 139, 141, 147).
U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions" (Issued Jul. 11, 2017)
The Invention Explained
- Problem Addressed: This patent, part of the same family, addresses the same technical problem as the ’768 Patent: the performance and physical limitations of parallel bus architectures in computers ('750 Patent, col. 1:33-2:67).
- The Patented Solution: The solution is likewise a system architecture based on high-speed, bidirectional serial communication using LVDS channels. This patent describes configurations where a CPU with an integrated interface controller connects directly to LVDS channels to convey PCI bus transactions, including address, data, and byte enable information bits, in serial form ('750 Patent, col. 4:1-49, Fig. 6).
- Technical Importance: The technology is foundational to modern high-speed computer interconnects, facilitating scalable performance improvements that were not possible with older parallel bus standards (Compl. ¶¶ 31-33).
Key Claims at a Glance
- The complaint asserts independent claims 25 and 46.
- Claim 25 (Printed Circuit Board):
- A printed circuit board
- An integrated CPU and interface controller in a single chip
- An LVDS channel directly extending from the CPU to convey address, data, and byte enable bits of a PCI bus transaction in serial form
- The LVDS channel uses two unidirectional, serial channels of multiple differential signal line pairs to convey data in opposite directions
- A socket for a system memory module directly coupled to the CPU
- Claim 46 (Computer):
- A computer with a CPU directly connected to an LVDS channel
- Using two sets of unidirectional, multiple, differential signal pairs
- To transmit encoded address and data bits of a PCI bus transaction in opposite directions
- System memory directly connected to the CPU
- A mass storage hard drive coupled to the CPU
- Other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially in opposite directions conveying USB protocol data packets
- The complaint reserves the right to assert additional claims (Compl. ¶¶ 157, 159, 161, 167).
U.S. Patent No. 8,756,359 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits" (Issued June 17, 2014)
- Technology Synopsis: This patent discloses a computer system using an LVDS channel that extends directly from the CPU, employing two sets of unidirectional differential signal line pairs to transmit data in opposite directions. The technology focuses on conveying data, including USB protocol data packets, through various connectors.
- Asserted Claims: The complaint asserts at least independent claim 6 (Compl. ¶¶ 176, 178, 180).
- Accused Features: The accused features include the CPU, connectors (including USB 3.x), and LVDS channels (such as PCIe and DMI) within the Accused Laptops, Desktops, and Servers (Compl. ¶¶ 176, 178, 180).
U.S. Patent No. 8,626,977 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits" (Issued Jan. 7, 2014)
- Technology Synopsis: This patent describes a computer with an integrated CPU and graphics subsystem in a single chip. The system includes an LVDS channel extending from the CPU to transmit PCI bus transaction data serially and other channels to convey USB protocol data, with the CPU also outputting digital video signals.
- Asserted Claims: The complaint asserts at least independent claim 1 (Compl. ¶¶ 190, 192).
- Accused Features: The accused features include the integrated Intel CPU/graphics subsystem, connectors (HDMI, DisplayPort, USB 3.x), and LVDS channels (PCIe) in the Accused Laptops and Desktops (Compl. ¶¶ 190, 192).
U.S. Reissue Patent No. RE44,739 - "Data Security Method and Device for Computer Modules" (Issued Jan. 28, 2014)
- Technology Synopsis: This patent relates to a computer with an integrated CPU and graphics controller. The system features various LVDS channels with at least two pairs of unidirectional lanes to transmit data (including USB 3.x data) in opposite directions, and connectors to couple to a console.
- Asserted Claims: The complaint asserts at least independent claim 18 (Compl. ¶¶ 202, 204).
- Accused Features: The accused features include the integrated Intel CPU/graphics controller, LVDS channels (PCIe, DMI, USB 3.x), and connectors (HDMI, DisplayPort) in the Accused Laptops and Desktops (Compl. ¶¶ 202, 204).
U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel" (Issued Mar. 10, 2015)
- Technology Synopsis: This patent claims a method of manufacturing a motherboard to improve data throughput. The method includes mounting an integrated CPU/interface controller, connecting an LVDS channel to it, and configuring the controller to adapt to different numbers of differential signal line pairs for conveying PCI bus transaction data.
- Asserted Claims: The complaint asserts at least independent claim 36 (Compl. ¶¶ 215, 217, 219).
- Accused Features: The infringement allegations target the manufacturing processes for the Accused Laptops, Desktops, and Servers, which allegedly involve mounting Intel CPU-controllers and connecting PCIe/DMI channels with multiple differential signal line pairs (Compl. ¶¶ 215, 217, 219).
U.S. Patent No. 9,529,769 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions" (Issued Dec. 27, 2016)
- Technology Synopsis: This patent claims a method for improving external peripheral data communication. The method includes obtaining an integrated CPU/graphics controller, connecting a unidirectional signal channel to it for video data, and providing LVDS channels through a connector to convey USB protocol data and digital video data.
- Asserted Claims: The complaint asserts at least independent claim 19 (Compl. ¶¶ 229, 231).
- Accused Features: The infringement allegations target the manufacturing processes for the Accused Laptops and Desktops, which allegedly involve using Intel core CPUs and providing connectors like Thunderbolt that convey both USB 3.x and DisplayPort signals (Compl. ¶¶ 229, 231).
U.S. Reissue Patent No. RE45,140 - "Data Security Method and Device for Computer Modules" (Issued Sep. 16, 2014)
- Technology Synopsis: This patent claims a method of improving computer performance by obtaining an integrated CPU/graphics controller and connecting LVDS channels directly to it. These channels use two unidirectional serial bit channels for transmitting data (e.g., PCIe/DMI) in opposite directions and provide connectors for external peripherals.
- Asserted Claims: The complaint asserts at least independent claim 35 (Compl. ¶¶ 241, 243).
- Accused Features: The infringement allegations target the manufacturing processes for the Accused Laptops and Desktops, which allegedly involve connecting PCIe/DMI channels directly to the Intel CPU-graphics chip and providing various connectors for peripherals (Compl. ¶¶ 241, 243).
U.S. Reissue Patent No. RE44,654 - "Data Security Method and Device for Computer Modules" (Issued Dec. 17, 2013)
- Technology Synopsis: This patent claims a method of increasing data communication speed by connecting a CPU directly to a peripheral bridge (PCH) on a circuit board via a DMI connection. The method also involves connecting an LVDS channel to the PCH for bidirectional data transmission and providing connectors for a console.
- Asserted Claims: The complaint asserts at least independent claim 23 (Compl. ¶¶ 253, 255, 257).
- Accused Features: The infringement allegations target the manufacturing processes for the Accused Laptops, Desktops, and Servers, which allegedly involve connecting an Intel core CPU to an Intel PCH via a DMI connection and connecting PCIe/USB 3.x channels to the PCH (Compl. ¶¶ 253, 255, 257).
III. The Accused Instrumentality
Product Identification
The complaint accuses ASUS Laptops, Desktops, Servers, and Motherboards, collectively referred to as the "Accused ASUS Products" (Compl. ¶48). Specific exemplary products include the ASUS ZenBook Pro 15 laptop, ASUS S340MF Tower desktop, ESC8000 G4 server, and PRIME H470-PLUS motherboard (Compl. ¶¶ 54, 68, 82, 105).
Functionality and Market Context
- The complaint alleges that the accused products incorporate Intel Core or Xeon processors that integrate a CPU, a graphics subsystem, and an interface controller, referred to as a "System Agent," on a single chip (Compl. ¶¶ 57, 71, 84). The complaint provides an Intel processor block diagram illustrating the System Agent's control over PCI Express and other data transmissions (Compl. ¶57, p. 14).
- These processors are allegedly connected to a peripheral bridge, such as an Intel Platform Controller Hub (PCH), via a Direct Media Interface (DMI) (Compl. ¶¶ 64, 78, 90). The complaint includes an Intel chipset diagram showing the CPU connected to the PCH via a DMI 3.0 link (Compl. ¶64, p. 19).
- The products are alleged to use various high-speed serial interconnects, such as PCI Express (PCIe), DMI, USB 3.x, and Thunderbolt, which function as the claimed "LVDS channels." These channels allegedly use pairs of unidirectional differential signal lanes to transmit data in opposite directions (Compl. ¶¶ 59, 61, 73, 75).
- Plaintiff alleges that ASUS is a global leader in the computer market, with sales generating billions of dollars in annual revenue (Compl. ¶¶ 40-42).
IV. Analysis of Infringement Allegations
'768 Patent Infringement Allegations
| Claim Element (from Independent Claim 33) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A computer comprising: a central processing unit (CPU) with an integrated interface controller | The accused products contain an Intel Core processor, which integrates a CPU with an interface controller within its "System Agent" to control PCIe and other data transmissions. The complaint presents a block diagram of the Intel processor architecture (Compl. ¶57, p. 14). | ¶¶ 56, 57, 136(b) | col. 36:50-52 |
| that is directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs to transmit encoded address and data bits | The CPU is allegedly connected to LVDS channels like PCIe and DMI, which use unidirectional pairs of lanes to transmit data, including PCI bus transaction data, in opposite directions. | ¶¶ 59, 136(b) | col. 36:53-58 |
| of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions | The PCIe and DMI interfaces are alleged to convey address and data bits of PCI bus transactions in serial form. | ¶¶ 35, 59, 136(b) | col. 36:58-60 |
| system memory directly coupled to the CPU | The accused products contain DDR4 system memory connected directly to the CPU. | ¶¶ 62, 136(c) | col. 36:61-62 |
| a mass storage hard drive coupled to the CPU | The accused products have mass storage, such as a PCIe NVMe SSD, coupled to the CPU. | ¶¶ 63, 136(d) | col. 36:63-64 |
| other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially in opposite directions | The accused products allegedly have other LVDS channels, including USB 3.x and Thunderbolt ports, which use pairs of unidirectional differential signal paths to transmit data serially. The complaint includes a table from the USB 3.0 specification showing this architecture (Compl. ¶36, p. 10). | ¶¶ 61, 136(e) | col. 36:65-67 |
'750 Patent Infringement Allegations
| Claim Element (from Independent Claim 25) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A printed circuit board comprising: an integrated central processing unit (CPU) and interface controller in a single chip | The accused motherboards (e.g., PRIME H470-PLUS) use an Intel Core processor, which allegedly integrates a CPU and an interface controller (the "System Agent") in a single chip. | ¶¶ 108, 109, 162(b) | col. 34:1-3 |
| a low voltage differential signal (LVDS) channel directly extending from the CPU to convey address bits, data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form | The CPU is allegedly connected to LVDS channels, such as PCIe and DMI, which convey PCI transaction data including address, data, and byte enable bits in a serial bit stream. | ¶¶ 111, 162(c) | col. 34:4-9 |
| through two unidirectional, serial channels of multiple differential signal line pairs to convey data in opposite directions | The accused PCIe and DMI channels allegedly use pairs of unidirectional lanes transmitting data in opposite directions. The complaint provides a diagram from an Intel guide illustrating dual unidirectional paths (Compl. ¶33, p. 8). | ¶¶ 33, 111, 162(c) | col. 34:10-13 |
| a socket for a system memory module directly coupled to the CPU | The accused motherboards have sockets for DDR4 system memory, which is directly coupled to the CPU. | ¶¶ 114, 162(d) | col. 34:14-15 |
Identified Points of Contention
- Scope Questions: A central question may be whether modern, standardized interconnects like PCIe, DMI, and USB 3.x, developed after the patent’s 1999 priority date, fall within the scope of the term "Low Voltage Differential Signal (LVDS) channel" as used in the patents. The defense may argue that "LVDS" refers to a specific, older technology, while the plaintiff may argue it is a generic term encompassing these modern standards.
- Technical Questions: The infringement theory hinges on mapping the claimed "CPU," "interface controller," and "peripheral bridge" to specific components in the accused products, namely the Intel Core/Xeon processor, the "System Agent" within the processor, and the separate Platform Controller Hub (PCH) chipset. A key technical question will be whether the System Agent is merely part of the CPU or if it functions as the claimed "interface controller," and whether the PCH, connected via DMI, meets the limitation of a "peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus" as required by claims like claim 10 of the ’768 Patent.
V. Key Claim Terms for Construction
The Term: "Low Voltage Differential Signal (LVDS) channel"
- Context and Importance: This term is the core of the claimed invention. Its construction will determine whether modern serial interconnects like PCIe, DMI, and USB 3.x, which are the basis of the infringement allegations, are covered by the patents. Practitioners may focus on this term because the complaint explicitly equates these modern standards with the claimed "LVDS channels" (Compl. ¶¶ 32, 35, 36).
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states, "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" ('977 Patent, col. 4:6-10). This language may support an interpretation that covers any interconnect using low voltage differential signaling, including PCIe and USB 3.x.
- Evidence for a Narrower Interpretation: The detailed embodiments describe a specific, proprietary bus (the "XPBus") that implements the LVDS channel concept ('977 Patent, Fig. 9; col. 15:15-24). The defense may argue the claims should be limited to this disclosed embodiment or technologies that are structurally equivalent, rather than broadly covering separately developed industry standards.
The Term: "directly connected" / "directly coupled"
- Context and Importance: The claims require a "direct" connection between components, such as a CPU and a peripheral bridge, or a CPU and an LVDS channel. The definition of "direct" is critical because the accused products use a multi-part architecture (CPU -> System Agent -> DMI -> PCH). The dispute will likely center on whether the DMI link between the CPU and the PCH constitutes an intervening component that breaks the "direct" connection required by some claims.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's goal was to replace the parallel PCI bus. The specification contrasts the invention with systems where a PCI-to-PCI bridge is used ('977 Patent, Fig. 5). Plaintiff may argue "direct" simply means "without an intervening PCI bus," a condition the DMI link meets.
- Evidence for a Narrower Interpretation: Figures in the patents, such as Figure 8A of the ’977 Patent, show the "Integrated CPU" and the "Host Interface Controller" as distinct but closely integrated blocks. The defense may argue that any intermediate bus, like DMI, prevents a connection from being "direct" in the ordinary sense of the word.
VI. Other Allegations
- Indirect Infringement: The complaint alleges inducement of infringement by providing instructions and direction to end users on how to use the Accused ASUS Products in an infringing manner (Compl. ¶130). For motherboards, inducement is alleged based on marketing them as "ready" for use with specified processors and memory and providing instructions on how to assemble them into a fully-functional, infringing computer system (Compl. ¶103, 143). Contributory infringement is alleged on the basis that the motherboards are a material part of the infringing system and have no substantial non-infringing use when combined with the instructed components (Compl. ¶¶ 3, 144-145).
- Willful Infringement: The complaint alleges willful infringement based on pre-suit knowledge of the patents. It specifically pleads that ACQIS sent a letter to ASUS on or around May 15, 2018, providing actual notice of the patents and their applicability to ASUS products (Compl. ¶¶ 51, 119). The complaint alleges that ASUS's continued infringement after this date was, at a minimum, objectively reckless (Compl. ¶¶ 121, 124).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of temporal scope and claim construction: can the term "LVDS channel," as described in patents with a 1999 priority date, be construed to read on modern, standardized interconnects like PCI Express and USB 3.x? The outcome will likely depend on whether the court interprets "LVDS" as a broad functional description of a signaling method or as a term of art tied to the specific technologies of that era.
- A second central question will be one of architectural mapping: does the asserted "CPU with an integrated interface controller directly connected to a peripheral bridge" claim structure map onto the accused products' architecture, which comprises an Intel processor (containing a CPU and a "System Agent") connected via a DMI link to a separate PCH chipset? This will require a detailed technical analysis of the function and relationship of each component.
- An evidentiary question regarding willfulness will be prominent: assuming infringement is found, do the facts surrounding the May 15, 2018 notice letter rise to the level of egregious conduct required to support enhanced damages, particularly given Plaintiff's assertion of Defendant's alleged willful blindness?