DCT

6:20-cv-00967

Acqis LLC v. Lenovo Group Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-00967, W.D. Tex., 05/28/2021
  • Venue Allegations: Plaintiff alleges venue is proper in any U.S. judicial district because Defendants are not U.S. residents.
  • Core Dispute: Plaintiff alleges that Defendant’s computer products, including laptops, desktops, and servers, infringe nine U.S. patents related to high-speed serial data communication technologies.
  • Technical Context: The technology concerns methods and systems for replacing older, parallel computer bus architectures with high-speed, low-power serial links, a foundational concept for modern standards like PCI Express and USB 3.x.
  • Key Procedural History: Plaintiff states it provided Defendant with actual notice of infringement of the patents-in-suit on or around May 15, 2018. The original complaint in this matter was filed on October 15, 2020. The complaint also notes a prior lawsuit involving related patents resulted in a jury verdict against IBM.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for ’768, ’750, ’359, ’977, ’797, ’140, ’654 Patents
2005-02-10 Priority Date for ’739 Patent
2005-03-31 Priority Date for ’769 Patent
2013-12-17 Issue Date for U.S. Patent No. RE44,654
2014-01-07 Issue Date for U.S. Patent No. 8,626,977
2014-01-28 Issue Date for U.S. Patent No. RE44,739
2014-06-17 Issue Date for U.S. Patent No. 8,756,359
2014-09-16 Issue Date for U.S. Patent No. RE45,140
2015-03-10 Issue Date for U.S. Patent No. 8,977,797
2016-12-27 Issue Date for U.S. Patent No. 9,529,768
2016-12-27 Issue Date for U.S. Patent No. 9,529,769
2017-07-11 Issue Date for U.S. Patent No. 9,703,750
2018-05-15 Plaintiff alleges providing actual notice of infringement to Lenovo
2020-10-15 Original Complaint Filing Date
2021-05-28 First Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. US9529768B2, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued December 27, 2016.

The Invention Explained

  • Problem Addressed: The complaint describes that traditional computer interconnections for standards like the Peripheral Component Interconnect (PCI) bus used parallel data transmission, which required a large number of signal channels and connector pins. This architecture was described as being power-inefficient, generating electrical noise, and not "cable friendly," making it difficult to employ more efficient low-voltage differential signal (LVDS) channels (Compl. ¶23).
  • The Patented Solution: The invention claims a computer system where the central processing unit (CPU) or a peripheral bridge is directly connected to an LVDS channel that uses pairs of unidirectional signal paths to serially transmit data bits of a PCI bus transaction in opposite directions (Compl. ¶26; ’359 Patent, Abstract). This serial architecture is designed to reduce pin count, lower power consumption, and enable higher-performance, scalable interconnections (’977 Patent, col. 3:55-67).
  • Technical Importance: This serial, differential signaling approach is described as a foundational technology that predates and is embodied in modern high-speed computer interfaces such as PCI Express (PCIe) and Universal Serial Bus 3.x (USB 3.x) (Compl. ¶¶37-40).

Key Claims at a Glance

  • The complaint asserts at least independent claim 33 (Compl. ¶117).
  • The essential elements of claim 33, as described in the complaint, include:
    • A computer running an operating system;
    • A CPU with an integrated interface controller directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs to transmit encoded address and data bits of a PCI bus transaction in opposite directions through different numbers of differential signal pairs;
    • System memory directly coupled to the CPU;
    • A mass storage hard drive coupled to the CPU; and
    • Other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially, including for USB 3.x, Thunderbolt, and PCIe channels.
  • The complaint reserves the right to assert additional claims (Compl. ¶118).

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

  • Patent Identification: U.S. Patent No. US9703750B2, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions," issued July 11, 2017.

The Invention Explained

This patent shares the same priority application and a nearly identical title with the ’768 Patent. It is directed at the same technical problem and proposes a similar solution involving the use of serial, bi-directional LVDS channels to replace parallel bus architectures for communicating PCI bus transactions (Compl. ¶27; ’359 Patent, col. 3:5-20).

Key Claims at a Glance

  • The complaint asserts at least independent claim 46 (Compl. ¶131).
  • The essential elements of claim 46, as described in the complaint, include:
    • A computer;
    • A CPU directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs to transmit encoded address and data bits of a PCI bus transaction in opposite directions;
    • System memory directly connected to the CPU;
    • A mass storage hard drive coupled to the CPU; and
    • Other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially, including USB protocol data packets via USB 3.x channels.
  • The complaint reserves the right to assert additional claims (Compl. ¶132).

U.S. Patent No. 8,756,359 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Patent Identification: U.S. Patent No. US8756359B2, "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued June 17, 2014.
  • Technology Synopsis: This patent relates to a computer system where a CPU has an LVDS channel extending directly from it, using unidirectional signal pairs to transmit data. The system also includes other LVDS channels, such as those coupled to USB 3.x connectors, to convey USB protocol data packets (Compl. ¶¶145, 147, 149).
  • Asserted Claims: Independent claim 6 is asserted (Compl. ¶145).
  • Accused Features: The accused features include the use of various connectors like USB 3.x and LVDS channels that extend directly from the CPU to transmit data in opposite directions (Compl. ¶¶145, 147, 149).

U.S. Patent No. 8,626,977 - "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits"

  • Patent Identification: U.S. Patent No. US8626977B2, "Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits," issued January 7, 2014.
  • Technology Synopsis: This patent claims a computer with an integrated CPU and graphics subsystem on a single chip. The system includes an LVDS channel extending from the CPU for PCI bus transactions and other serial channels coupled to connectors, such as for USB 3.x, that convey USB protocol data packets (Compl. ¶¶159, 161).
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶159).
  • Accused Features: The allegations target computers with integrated CPU and graphics subsystems, LVDS channels (e.g., PCIe) for PCI transactions, and other serial channels (e.g., USB 3.x) (Compl. ¶¶159, 161).

U.S. Patent No. RE44,739 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: U.S. Patent No. USRE044739E1, "Data Security Method and Device for Computer Modules," issued January 28, 2014.
  • Technology Synopsis: This patent is directed to a computer with an integrated CPU and graphics controller on a single chip. The chip is coupled to differential signal channels (e.g., HDMI, DisplayPort) for video data and various LVDS channels (e.g., USB 3.x) for transmitting data in opposite directions (Compl. ¶¶171, 173).
  • Asserted Claims: Independent claim 18 is asserted (Compl. ¶171).
  • Accused Features: The allegations target computers with integrated CPU/graphics controllers, channels for digital video display, and various LVDS channels including USB 3.x ports (Compl. ¶¶171, 173).

U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"

  • Patent Identification: U.S. Patent No. US8977797B2, "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel," issued March 10, 2015.
  • Technology Synopsis: This patent claims a method of improving data throughput on a motherboard by mounting an integrated CPU and interface controller and connecting an LVDS channel with multiple differential signal line pairs directly to it. The interface controller is configured to adapt to different numbers of line pairs to convey PCI bus transactions (Compl. ¶¶184, 186, 188).
  • Asserted Claims: Method claim 36 is asserted (Compl. ¶184).
  • Accused Features: The accused feature is the manufacturing process of the Accused Products, which allegedly involves mounting integrated CPU-controllers and connecting them to multi-lane PCIe channels to convey PCI data (Compl. ¶¶184, 186, 188).

U.S. Patent No. 9,529,769 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions"

  • Patent Identification: U.S. Patent No. US9529769B2, "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction In Opposite Directions," issued December 27, 2016.
  • Technology Synopsis: This patent claims a method of improving external peripheral data communication by obtaining an integrated CPU and graphics controller on a single chip and connecting it to multiple signal channels. These channels include a unidirectional channel for digital video data and an LVDS channel with two unidirectional serial bit channels for USB protocol data (Compl. ¶¶198, 200).
  • Asserted Claims: Method claim 19 is asserted (Compl. ¶198).
  • Accused Features: The manufacturing process is accused, specifically the steps of using an integrated CPU/graphics chip and connecting it to channels for HDMI/DisplayPort and connectors like Thunderbolt/USB 3.x (Compl. ¶¶198, 200).

U.S. Patent No. RE45,140 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: U.S. Patent No. USRE045140E1, "Data Security Method and Device for Computer Modules," issued September 16, 2014.
  • Technology Synopsis: This patent is directed at a method of improving computer performance by obtaining an integrated CPU/graphics controller and connecting it to multiple channels. The channels include an LVDS channel (e.g., PCIe/DMI) and a differential signal channel (e.g., HDMI/DisplayPort) for video output (Compl. ¶¶210, 212).
  • Asserted Claims: Method claim 35 is asserted (Compl. ¶210).
  • Accused Features: The accused act is the manufacturing process, which allegedly includes using integrated Intel CPUs and connecting them to PCIe/DMI and HDMI/DisplayPort channels (Compl. ¶¶210, 212).

U.S. Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"

  • Patent Identification: U.S. Patent No. USRE044654E1, "Data Security Method and Device for Computer Modules," issued December 17, 2013.
  • Technology Synopsis: This patent claims a method of increasing data communication speed by connecting a CPU directly to a peripheral bridge (e.g., an Intel PCH) on a circuit board. An LVDS channel is then connected directly to this peripheral bridge for bi-directional data transmission (Compl. ¶¶222, 224, 226).
  • Asserted Claims: Method claim 23 is asserted (Compl. ¶222).
  • Accused Features: The accused feature is the manufacturing process, which allegedly involves connecting an Intel CPU to an Intel PCH via a DMI connection and connecting PCIe and USB 3.x channels directly to that PCH (Compl. ¶¶222, 224, 226).

III. The Accused Instrumentality

Product Identification

The complaint identifies the "Accused Lenovo Products," which include laptops (ThinkPad®, YOGA®, Legion®), desktops (ThinkStation®, ThinkCentre®), and servers (ThinkSystem®, ThinkServer®) (Compl. ¶¶49-52).

Functionality and Market Context

The complaint alleges that the Accused Products, exemplified by the ThinkPad P1 laptop, ThinkStation P340 desktop, and ThinkSystem SR650 server, incorporate Intel Core or Xeon processors (Compl. ¶¶60, 74, 88). These processors are alleged to integrate the central processing unit, graphics subsystem, and interface controllers for various data transmission protocols onto a single chip (Compl. ¶¶61, 75). The complaint provides a block diagram from an Intel datasheet illustrating the architecture of a 10th Generation Intel® Core™ Processor, which shows a CPU core section directly connected to a "System Agent" that controls PCIe and other data transmissions (Compl. ¶61 & p. 17). The products are alleged to use these integrated processors to connect directly to LVDS channels such as PCIe, DMI, USB 3.x, HDMI, and DisplayPort, which employ pairs of unidirectional, differential signal lanes to transmit data serially in opposite directions (Compl. ¶¶63, 65, 77, 79, 90, 91). Plaintiff alleges that Defendant's sales of these products generate billions of dollars in annual revenue (Compl. ¶46).

IV. Analysis of Infringement Allegations

'768 Patent Infringement Allegations

Claim Element (from Independent Claim 33) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer running the Windows® operating system The accused ThinkPad® P1 laptop is a computer system that runs the Windows operating system ¶117a ’977 Patent, col. 2:41-43
a central processing unit (CPU) with an integrated interface controller that is directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs to transmit encoded address and data bits of a PCI bus transaction in opposite directions through different numbers of differential signal pairs The Intel® Core processor in the ThinkPad® P1 allegedly integrates the CPU and interface controller. This integrated unit is allegedly connected to PCIe channels, which are LVDS channels that use pairs of unidirectional lanes to convey PCI bus transactions serially. The complaint includes a diagram showing the processor connected to PCIe lanes (Compl. ¶63 & p. 19). ¶117b ’977 Patent, col. 5:36-41
system memory directly coupled to the CPU The accused ThinkPad® P1 laptop allegedly has DDR4 system memory connected directly to the CPU ¶117c ’977 Patent, Fig. 8A
a mass storage hard drive coupled to the CPU The accused ThinkPad® P1 laptop allegedly has a mass storage hard drive, such as a PCIe SSD, coupled to the CPU ¶117d ’977 Patent, Fig. 8A
other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially in opposite directions constituting point-to-point data communication links, including various USB 3.x channels, Thunderbolt connectors, and additional PCIe channels The Intel processors in the accused laptops allegedly connect to LVDS channels that convey USB data packets through pairs of unidirectional differential signal paths in opposite directions, including USB 3.x ports, Thunderbolt, and additional PCIe channels ¶117e ’977 Patent, Claim 11

'750 Patent Infringement Allegations

Claim Element (from Independent Claim 46) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer The accused ThinkStation P340 Workstation is a computer running the Windows® operating system ¶133a ’977 Patent, col. 2:41-43
a CPU directly connected to an LVDS channel using two sets of unidirectional, multiple, differential signal pairs to transmit encoded address and data bits of a PCI bus transaction in opposite directions The Intel® processor in the ThinkStation P340 is allegedly connected to DMI and PCIe channels. The complaint alleges these are LVDS channels that use pairs of unidirectional lanes to serially convey PCI bus transactions. An Intel block diagram shows the processor's direct PCIe connection (Compl. ¶77 & p. 28). ¶133b ’977 Patent, col. 5:36-41
system memory directly connected to the CPU The accused ThinkStation P340 allegedly has DDR4 system memory connected directly to the CPU ¶133c ’977 Patent, Fig. 8A
a mass storage hard drive coupled to the CPU The accused ThinkStation P340 allegedly has a mass storage hard drive, such as a PCIe NVMe SSD, coupled to the CPU ¶133d ’977 Patent, Fig. 8A
other LVDS channels that use two sets of unidirectional, differential signal pairs to transmit data serially in opposite directions constituting point-to-point data communication links that convey USB protocol data packets, including various USB 3.x channels The Intel processors in the accused desktops allegedly also connect to LVDS channels that convey USB data packets through pairs of unidirectional differential signal paths in opposite directions, including via USB 3.x ports ¶133e ’977 Patent, Claim 11

Identified Points of Contention

  • Scope Questions: A primary question may be whether the term "directly connected" as used in the patents reads on the accused architecture, where a CPU is connected to a Platform Controller Hub (PCH) via a Direct Media Interface (DMI) bus, which in turn connects to other peripherals (Compl. ¶68). The analysis may focus on whether the DMI constitutes an intervening bus that negates a "direct" connection as understood in the context of the patents.
  • Scope Questions: The infringement theory relies on modern serial standards like PCIe and USB 3.x, which post-date the patents' 1999 priority date, falling within the scope of claim terms such as "PCI bus transaction" and "LVDS channel" (Compl. ¶¶37, 40). A central dispute may be whether the claims are broad enough to cover these subsequently developed technologies.
  • Technical Questions: The complaint alleges that the accused products' PCIe channels transmit "encoded address and data bits of a PCI bus transaction" (Compl. ¶117b). A technical question for the court will be whether the data packets used in the PCIe protocol (e.g., Transaction Layer Packets) are functionally and structurally equivalent to the serialized "PCI bus transaction" contemplated by the patents.

V. Key Claim Terms for Construction

The Term: "directly connected" / "directly extending from"

  • Context and Importance: The infringement theory hinges on whether components like the CPU are "directly connected" to LVDS channels. Defendant may argue that intermediate logic or buses within the processor package or chipset, such as the DMI connecting the CPU to the PCH (Compl. ¶68), break this direct connection. The construction of this term is therefore critical to determining whether the accused architecture meets this claim limitation.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The ’977 Patent specification describes embodiments with a "single chip fully integrated" CPU, core logic, graphics controller, and interface controller (’977 Patent, Fig. 8B). This may support a construction where components integrated into a single package are considered "directly connected," even with internal buses.
    • Evidence for a Narrower Interpretation: The ’977 Patent also depicts embodiments with distinct Host Interface Controllers and Peripheral Interface Controllers connected by an "XPBus" (’977 Patent, Fig. 9). This could support an argument that "directly" requires a point-to-point link without any intermediate bus protocol, such as the DMI shown in the accused products.

The Term: "LVDS channel"

  • Context and Importance: The applicability of the patents to modern standards like PCIe and USB 3.x depends on whether their physical layers constitute an "LVDS channel." Practitioners may focus on this term because the specific electrical characteristics of modern standards may differ from those of LVDS standards from the priority period.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification of the related ’977 Patent explicitly states: "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" (’977 Patent, col. 4:3-6). This language may strongly support a broad construction covering any low-voltage differential signaling scheme.
    • Evidence for a Narrower Interpretation: An opposing argument might focus on the specific examples and figures in the patent, which describe a particular "XPBus" protocol (’977 Patent, Fig. 9), to argue that "LVDS channel" should be limited to signaling schemes with similar characteristics to those known at the time of the invention.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement, stating that Defendant actively promotes the accused products for the U.S. market, provides instructions to end users, and configures the products in such a way that direct infringement "necessarily occurs upon operation" (Compl. ¶¶107, 111). Contributory infringement is also alleged on the basis that the products are material parts of a computer system and not staple articles of commerce with substantial non-infringing uses (Compl. ¶107).
  • Willful Infringement: The complaint alleges willful infringement based on Defendant's alleged pre-suit knowledge of the patents. Plaintiff alleges it provided Defendant with actual notice of the ACQIS Patents and the alleged infringement via a letter on or around May 15, 2018, but that Defendant continued to infringe (Compl. ¶¶101-106).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope and technological evolution: can claim terms rooted in the 1999 state of the art, such as "PCI bus transaction" and "LVDS channel," be construed to encompass modern, packet-based serial standards like PCI Express and USB 3.x that were developed after the patents' priority date? The patent's own definition of "LVDS" may be a key piece of evidence in this analysis.
  • A second central issue will be one of architectural interpretation: does the term "directly connected" require a point-to-point link without any intermediate bus, or can it cover the accused products' architecture where a CPU communicates with I/O controllers through an on-package interface like the DMI? The outcome of this construction could be dispositive for infringement.
  • A key question for damages will be willfulness: did Defendant's alleged conduct after receiving a specific notice letter in May 2018 constitute willful infringement, potentially leading to enhanced damages? This will depend on the sufficiency and content of the notice and Defendant's subsequent actions.