DCT

6:20-cv-00968

Acqis LLC v. Wistron Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-00968, W.D. Tex., 10/15/2020
  • Venue Allegations: Venue is alleged to be proper because the Defendants are foreign corporations not resident in the United States and may therefore be sued in any judicial district.
  • Core Dispute: Plaintiff alleges that Defendants' servers and related computer products infringe a portfolio of eight patents related to high-performance, low-power interconnection technologies that utilize serial data transmission over Low Voltage Differential Signal (LVDS) channels.
  • Technical Context: The technology addresses methods for increasing data transmission speed between core computing components, a foundational element of modern standards like PCI Express (PCIe) and Universal Serial Bus (USB) 3.x.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendants with actual notice of infringement of all asserted patents on or around July 17, 2018. The complaint also notes a prior lawsuit involving related ACQIS patents resulted in a significant jury verdict against IBM, a fact which may be relevant to the allegations of willful infringement.

Case Timeline

Date Event
1999-05-14 Earliest Patent Priority Date for all asserted patents
2010-03-09 U.S. Patent No. 7,676,624 Issued
2011-10-18 U.S. Patent No. 8,041,873 Issued
2013-08-27 U.S. Patent No. RE44,468 Issued
2013-12-17 U.S. Patent No. RE44,654 Issued
2015-03-10 U.S. Patent No. 8,977,797 Issued
2016-12-27 U.S. Patent No. 9,529,768 Issued
2017-07-11 U.S. Patent No. 9,703,750 Issued
2018-07-10 U.S. Patent No. RE46,947 Issued
2018-07-17 Plaintiff allegedly provided Defendants with actual notice of infringement
2020-10-15 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions”

  • Patent Identification: U.S. Patent No. 9529768, entitled “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions,” issued on December 27, 2016 (Compl. ¶24).
  • The Invention Explained:
    • Problem Addressed: The patent addresses the limitations of traditional computer interconnections, which used parallel peripheral component interconnect (PCI) buses. These parallel buses required a large number of signal channels and connector pins, making them power-inefficient, noisy, and difficult to implement with more "cable friendly" technologies like Low Voltage Differential Signal (LVDS) channels (Compl. ¶21).
    • The Patented Solution: The invention proposes a computer system architecture where a CPU or peripheral bridge is directly connected to an LVDS channel. This channel communicates the data, address, and control bits of a PCI bus transaction as a serial bit stream, using pairs of unidirectional differential signal paths to transmit data in opposite directions. This approach reduces pin count, consumes less power, and generates less noise while increasing data transmission speed (Compl. ¶1, ¶21; ’624 Patent, col. 6:23-25).
    • Technical Importance: This serial, differential signaling architecture is described as foundational to modern high-speed data transmission standards like PCI Express and USB 3.x, which have become ubiquitous in the computer industry (Compl. ¶1, ¶34).
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 13 (’971 Patent, col. 6:50-65).
    • The essential elements of claim 13, as characterized in the complaint, include:
      • A computer comprising,
      • a central processing unit (CPU) with an integrated interface controller in a single chip;
      • a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream;
      • wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction; and
      • system memory directly coupled to the CPU and interface controller (Compl. ¶90).
    • The complaint reserves the right to assert additional claims (Compl. ¶91).

U.S. Patent No. 9,703,750 - “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions”

  • Patent Identification: U.S. Patent No. 9703750, entitled “Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions,” issued on July 11, 2017 (Compl. ¶25).
  • The Invention Explained:
    • Problem Addressed: As with the ’768 patent, this invention addresses the technical challenges of parallel bus architectures, such as high pin counts, power consumption, and noise, which hindered the adoption of high-speed LVDS channels for interconnections (Compl. ¶21).
    • The Patented Solution: This patent also describes a system using a direct connection between a CPU's integrated interface controller and an LVDS channel for serializing PCI bus transactions. It adds the use of Phase-Locked Loop (PLL) clock circuitry within the interface controller to generate different clock frequencies, allowing the system to configure the LVDS channel to operate at different data transfer rates based on those frequencies. It also claims a connector for a second LVDS channel for protocols like USB (’971 Patent, col. 6:50-65; Compl. ¶101).
    • Technical Importance: The claimed use of variable clock frequencies generated by PLLs to control data rates over serial links is a key feature of modern high-speed I/O technologies like PCIe, which adjust link speeds for power management and performance optimization (Compl. ¶58, ¶59).
  • Key Claims at a Glance:
    • The complaint asserts at least independent claim 4 (’971 Patent, col. 6:50-65).
    • The essential elements of claim 4, as characterized in the complaint, add several features to the core invention, including:
      • The interface controller comprises Phase-Locked Loop (PLL) clock circuitry capable of generating different clock frequencies;
      • The interface controller configures the first LVDS channel to convey the PCI bus transaction at different data transfer rates based on the different clock frequencies; and
      • The interface controller comprises a connector adapted to convey a serial bit stream of Universal Serial Bus (USB) protocol data packets in a second LVDS channel (Compl. ¶101).
    • The complaint reserves the right to assert additional claims (Compl. ¶102).

Multi-Patent Capsule: U.S. Patent No. 8,977,797

  • Patent Identification: U.S. Patent No. 8977797, “Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel,” issued March 10, 2015 (Compl. ¶26).
  • Technology Synopsis: This patent claims a method of manufacturing a computer that improves data throughput. The method involves connecting a CPU directly to a peripheral bridge on a circuit board and connecting an LVDS channel, comprising two unidirectional serial channels, directly to that bridge to convey encoded PCI bus transactions (Compl. ¶113).
  • Asserted Claims: At least independent claim 7 (Compl. ¶113).
  • Accused Features: The manufacturing process of the Accused Servers, which allegedly includes the claimed steps of connecting the CPU, peripheral bridge, and LVDS channel on a printed circuit board (Compl. ¶70, ¶113).

Multi-Patent Capsule: U.S. Patent No. 8,041,873

  • Patent Identification: U.S. Patent No. 8041873, “Multiple Module Computer System and Method Including Differential Signal Channel Comprising Unidirectional Serial Bit Channels to Transmit Encoded Peripheral Component Interconnect Bus Transaction Data,” issued October 18, 2011 (Compl. ¶27).
  • Technology Synopsis: This patent describes a multi-module computer system where computer modules are insertable into a console. The system uses an LVDS channel with two sets of unidirectional, multiple serial bit channels to communicate encoded PCI bus transaction data in opposite directions (Compl. ¶124).
  • Asserted Claims: At least independent claim 77 (Compl. ¶124).
  • Accused Features: The Accused Servers are alleged to be computer systems with processing units, memory, and an LVDS channel (e.g., PCIe) for communicating PCI transactions, and a serial communication controller for coupling to a console or rack (Compl. ¶124(a)-(f)).

Multi-Patent Capsule: U.S. Patent No. RE44,468

  • Patent Identification: U.S. Patent No. RE44468, “Data Security Method and Device for Computer Modules,” issued August 27, 2013 (Compl. ¶28).
  • Technology Synopsis: This patent claims a computer having a CPU directly connected to an LVDS channel. The channel comprises two sets of multiple, unidirectional, serial bit channels to convey an encoded serial bit stream of a PCI bus transaction in opposite directions (Compl. ¶135).
  • Asserted Claims: At least independent claim 45 (Compl. ¶135).
  • Accused Features: The Accused Servers’ architecture, including their CPUs being directly connected to LVDS channels (e.g., PCIe) that convey PCI transactions (Compl. ¶135(a)-(d)).

Multi-Patent Capsule: U.S. Patent No. RE44,654

  • Patent Identification: U.S. Patent No. RE44654, “Data Security Method and Device for Computer Modules,” issued December 17, 2013 (Compl. ¶29).
  • Technology Synopsis: This patent claims a method of manufacturing a computer that involves connecting a CPU to a peripheral bridge, connecting a first LVDS channel to that bridge, and providing a connector for a second LVDS channel to couple to a console, with both channels conveying PCI bus transaction data (Compl. ¶147).
  • Asserted Claims: At least independent claim 14 (Compl. ¶147).
  • Accused Features: The manufacturing process of the Accused Servers, which allegedly involves connecting a CPU, peripheral bridge, and LVDS channels, and providing a connector for console communication (Compl. ¶147(a)-(g)).

Multi-Patent Capsule: U.S. Patent No. RE46,947

  • Patent Identification: U.S. Patent No. RE46947, “Data Security Method and Device for Computer Modules,” issued July 10, 2018 (Compl. ¶30).
  • Technology Synopsis: This patent claims a computer where a CPU with an interface controller has a first LVDS channel directly extending from it. The channel uses two unidirectional serial bit channels, each comprising four or more differential signal pairs, to convey encoded PCI bus transaction data (Compl. ¶158).
  • Asserted Claims: At least independent claim 54 (Compl. ¶158).
  • Accused Features: The Accused Servers' CPUs, which comprise an interface controller, are allegedly connected to a first LVDS channel (e.g., PCIe) and a second LVDS channel coupled to a connector (Compl. ¶158(a)-(e)).

Multi-Patent Capsule: U.S. Patent No. 7,676,624

  • Patent Identification: U.S. Patent No. 7676624, “Multiple Module Computer System and Method Including Differential Signal Channel Comprising Undirectional [sic] Serial Bit Channels,” issued March 9, 2010 (Compl. ¶31).
  • Technology Synopsis: This patent describes a computer system comprising a console with multiple coupling sites and a plurality of independent computer modules. Each module has an interface controller coupled to a differential signal channel for transmitting encoded PCI bus transaction data in opposite directions (Compl. ¶168).
  • Asserted Claims: At least independent claim 11 (Compl. ¶168).
  • Accused Features: The Accused Servers, when combined with WiRack racks, are alleged to form a computer system with a console and multiple independent computer modules, where each module's interface controller couples to a differential signal channel (Compl. ¶168(a)-(f)).

III. The Accused Instrumentality

  • Product Identification: The accused products are Wiwynn-branded servers and related accessories, including those sold under the OCP, WiRack 19, and WiRack 21 Server brand names (Compl. ¶44). The complaint uses the WiRack 19 Server SV302G3 Series and the WiRack21 Storage ST7000G2/SV7000G2 Series as illustrative examples (Compl. ¶44-45).
  • Functionality and Market Context: The complaint alleges the Accused Servers are modular computer systems that function as cloud IT infrastructure for data centers (Compl. ¶41, ¶50). A block diagram provided in the complaint illustrates an Intel Xeon Scalable Processor with integrated PCIe and DMI channels connected to a chipset (Compl. ¶51, p. 14). Functionally, they are alleged to employ Intel processors (e.g., Xeon Scalable or Broadwell-DE) with integrated interface controllers (Compl. ¶51, ¶62). These controllers are alleged to connect directly to various LVDS channels, such as PCIe, Intel's Direct Media Interface (DMI), and USB 3.x ports, which convey data in serial streams using unidirectional pairs of lanes (Compl. ¶53-54, ¶64-65). The complaint further alleges that the servers' chipsets (e.g., Intel C621) contain Integrated Clock Controllers with Phase-Locked Loop (PLL) circuitry that generate different clock frequencies to manage data transfer rates for PCI and USB transactions (Compl. ¶58, ¶68).

IV. Analysis of Infringement Allegations

  • ’768 Patent Infringement Allegations
Claim Element (from Independent Claim 13) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer The WiRack 19 Server SV302G3 and WiRack21 Storage ST7000G2/SV7000G2 Series are computers (Compl. ¶90(a)). ¶90 ’624 Patent, col. 1:57
comprising a central processing unit (CPU) with an integrated interface controller in a single chip The Accused Servers use Intel Xeon or Broadwell-DE processors, which have integrated interface controllers on a single chip to drive the connected PCIe channels (Compl. ¶51, ¶62). ¶51, ¶62, ¶90 ’624 Patent, col. 8:8
a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller to convey address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial bit stream The Intel processors directly connect to PCIe channels, which are LVDS channels that convey data bits, address bits, and byte enable information bits of a PCI bus transaction in a serial bit stream (Compl. ¶36, ¶53, ¶64). ¶36, ¶53, ¶90 ’624 Patent, col. 5:51
wherein the first LVDS channel comprises first unidirectional, multiple, differential signal pairs to convey data in a first direction and second unidirectional, multiple, differential signal pairs to convey data in a second, opposite direction PCI Express connections are alleged to be LVDS channels that use pairs of unidirectional, differential signal lanes to convey information in opposite directions (Compl. ¶36). A diagram illustrates this dual unidirectional path concept (Compl. ¶34). ¶34, ¶36, ¶53, ¶90 ’624 Patent, col. 6:23
system memory directly coupled to the CPU and interface controller The Accused Servers have system memory (e.g., DDR4 DIMMs) directly coupled to the CPU (Compl. ¶55, ¶66). ¶55, ¶66, ¶90 ’624 Patent, col. 10:40
  • ’750 Patent Infringement Allegations
Claim Element (from Independent Claim 4) Alleged Infringing Functionality Complaint Citation Patent Citation
[Elements (a)-(d) are substantially similar to those analyzed for the ’768 Patent] [Functionality for elements (a)-(d) is as described in the claim chart for the ’768 Patent] ¶101 ’624 Patent, col. 5:51
the interface controller of the... computer comprises Phase-Locked Loop (PLL) clock circuitry capable of generating different clock frequencies The Intel C621 PCH and Xeon processors used in the Accused Servers contain an Integrated Clock Controller (ICC) that includes PLL circuitry, which generates different clock frequencies for PCIe and USB channels (Compl. ¶58, ¶59, ¶68). ¶58, ¶59, ¶68, ¶101 ’624 Patent, col. 12:20
the interface controller... configures the first LVDS channel to convey the PCI bus transaction at different data transfer rates based on the different clock frequencies generated by the PLL clock circuitry The ICC with PLL circuitry is alleged to generate different clock frequencies to convey PCI bus transactions through PCIe channels based on those different clock frequencies (Compl. ¶58, ¶59). ¶58, ¶59, ¶101 ’624 Patent, col. 6:26
and the interface controller... comprises a connector adapted to convey a serial bit stream of Universal Serial Bus (USB) protocol data packets in a second Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs that transmit data in opposite directions The Accused Servers comprise USB 3.x ports, which are described as LVDS channels using two unidirectional, differential signal pairs to transmit USB protocol data packets in opposite directions (Compl. ¶37, ¶54, ¶65). A table from the USB 3.0 Specification is provided as evidence (Compl. ¶37, p. 10). ¶37, ¶54, ¶65, ¶101 ’624 Patent, col. 15:43
  • Identified Points of Contention:
    • Scope Questions: The patents have a 1999 priority date, while the accused technologies like PCI Express and USB 3.x were standardized later. A primary question for the court will be whether implementing these subsequent industry standards falls within the literal scope of claim terms like "Low Voltage Differential Signal (LVDS) channel" and "Peripheral Component Interconnect (PCI) bus transaction." The complaint's assertion that PCIe "post-dates Dr. Chu's inventions but embodies" them suggests this will be a central dispute (Compl. ¶34).
    • Technical Questions: What evidence does the complaint provide that the interface controller performs the active step of "configuring" the LVDS channel for different data rates, as required by claim 4 of the ’750 patent? A potential dispute may arise over whether the accused devices perform this claimed function or simply operate at pre-set, standard-defined rates without performing a distinct configuration step as taught by the patent.

V. Key Claim Terms for Construction

  • The Term: "Low Voltage Differential Signal (LVDS) channel"

  • Context and Importance: This term is central to the asserted claims. The outcome of the case may depend on whether modern high-speed serial interconnects like PCIe, DMI, and USB 3.x are considered "LVDS channels" within the meaning of the patents. Practitioners may focus on this term because the complaint's infringement theory relies on mapping these modern standards, developed after the 1999 priority date, onto the claimed technology.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification of a related patent states, "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" (’624 Patent, col. 4:60-63). This language may support a functional definition covering any technology that uses low-voltage, differential signaling.
    • Evidence for a Narrower Interpretation: The background section frames the problem in terms of making interconnections more "cable friendly" (’624 Patent, col. 3:45-48). A defendant may argue this context limits the term to external cabling applications or to the specific electrical characteristics of LVDS standards prevalent in 1999, potentially distinguishing them from the on-chip and backplane PHYs used for modern PCIe or DMI.

  • The Term: "directly extending from the interface controller"

  • Context and Importance: This phrase defines the claimed system architecture. Infringement may hinge on the degree of directness between the processor's integrated controller and the physical I/O lanes. The complaint uses block diagrams from Intel to show this connection (Compl. p. 14).

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: A patentee may argue "directly" is used to distinguish the invention from the prior art, such as systems using a PCI-to-PCI bridge, and should be construed to mean a connection without an intervening bus that changes the protocol or bus hierarchy (’624 Patent, col. 3:9-25).
    • Evidence for a Narrower Interpretation: A defendant may argue that "directly" requires an immediate physical and electrical connection without any intervening logic, multiplexers, or physical layer circuitry inside the processor silicon. The patent's description of a "host interface controller" as a discrete block (e.g., ’624 Patent, Fig. 9) could be used to argue that the integrated nature of the accused processors is fundamentally different from the architecture disclosed.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement based on Defendants actively promoting the Accused Servers for the U.S. market, providing instructions to end users, and configuring the servers such that their normal, intended operation is infringing (Compl. ¶80-83). Contributory infringement is alleged on the grounds that the products are especially adapted for use in an infringing manner and are not staple articles of commerce with substantial non-infringing uses (Compl. ¶85).
  • Willful Infringement: The willfulness allegation is based on alleged pre-suit knowledge. The complaint states that ACQIS sent a letter providing actual notice of infringement of all asserted patents to Wiwynn on or around July 17, 2018, and that Wiwynn did not respond and continued its allegedly infringing activities (Compl. ¶74, ¶76, ¶79).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of temporal scope and equivalents: can claim terms from patents with a 1999 priority date, such as "LVDS channel" and "PCI bus transaction," be construed to literally cover modern, standardized interfaces like PCI Express and USB 3.x that were developed after the inventions? This question may require the court to consider whether the accused technologies represent a mere implementation of the patented concept or a distinct technological evolution.
  • A key evidentiary question will be one of architectural interpretation: does the integrated nature of the accused Intel processors, where I/O control is part of a complex system-on-a-chip, satisfy the claims' requirement for a "direct" connection from an "interface controller" to a channel? The analysis will likely depend on a detailed technical examination of the processors' internal design versus the architecture disclosed in the patents.
  • A central issue for damages will be willfulness: did the Defendants act recklessly by allegedly continuing to sell the Accused Servers after receiving a detailed notice letter in 2018 that identified the specific patents and accused products? The Plaintiff's emphasis on a prior successful lawsuit against IBM may be used to argue that the validity and applicability of the patent portfolio were already established, potentially increasing the risk for the Defendants.