DCT

6:20-cv-01041

The California Institute of T

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Amended Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-01041, W.D. Tex., 03/19/2021
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because HP maintains a regular and established place of business in the district, including an Austin office with over 150 employees and multiple data centers, and has committed alleged acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Wi-Fi-enabled products that comply with the IEEE 802.11n, 802.11ac, and 802.11ax standards infringe five patents related to high-performance, low-complexity error correction codes.
  • Technical Context: The technology involves Irregular Repeat-Accumulate (IRA) and Repeat-Accumulate (RA) codes, which are advanced error-correction methods designed to enable reliable data transmission at high speeds, a critical function in modern wireless communications.
  • Key Procedural History: The complaint notes that in January 2020, a jury in the Central District of California found that Apple and Broadcom infringed three of the patents-in-suit ('710, '032, and '781) and awarded Caltech over $1.1 billion in damages. The complaint also states that ten inter partes review (IPR) petitions filed by Apple against the patents were either denied institution or resulted in the Patent Trial and Appeal Board (PTAB) upholding the patentability of the challenged claims.

Case Timeline

Date Event
1999-08-18 Priority Date (U.S. Patent No. 7,716,552)
2000-05-18 Priority Date (U.S. Patent Nos. 7,116,710; 7,421,032; 7,916,781; 8,284,833)
2000-09-01 Inventors publish paper on Irregular Repeat-Accumulate Codes
2006-10-03 Issue Date (U.S. Patent No. 7,116,710)
2008-09-02 Issue Date (U.S. Patent No. 7,421,032)
2010-05-11 Issue Date (U.S. Patent No. 7,716,552)
2011-03-29 Issue Date (U.S. Patent No. 7,916,781)
2012-10-09 Issue Date (U.S. Patent No. 8284833)
2016-05-01 Prior litigation filed (Caltech v. Apple and Broadcom)
2020-01-29 Jury verdict in Caltech v. Apple and Broadcom
2021-03-19 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,116,710 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

The Invention Explained

  • Problem Addressed: The patent addresses the complexity of prior art "turbo codes," which, while enabling communication near theoretical channel capacity, required relatively complex encoding and decoding algorithms that could be difficult to implement efficiently (ʼ710 Patent, col. 1:36-39).
  • The Patented Solution: The invention discloses a "turbo-like" coding system composed of serially connected components. An "outer coder" first takes a block of data bits, repeats them an irregular number of times according to a "degree profile," and then scrambles (interleaves) the repeated bits. This output is then fed to an "inner coder," which is a simple, rate-one encoder (such as an accumulator) that performs recursive additions. This two-stage process creates what are known as Irregular Repeat-Accumulate (IRA) codes, which are designed to achieve high performance with simpler hardware than conventional turbo codes (’710 Patent, Abstract; col. 2:32-65).
  • Technical Importance: This architecture provided a method for creating powerful error-correction codes that were less computationally intensive to encode and decode, making them practical for widespread use in high-volume, cost-sensitive wireless devices (Compl. ¶21).

Key Claims at a Glance

  • The complaint asserts at least dependent claim 20, which incorporates independent claim 15 (Compl. ¶32).
  • The essential elements of asserted claim 20 are an apparatus (a coder) comprising:
    • A first coder configured to receive a stream of bits, repeat the bits irregularly, and scramble the repeated bits, where this first coder is a "low-density generator matrix [LDGM] coder."
    • A second coder configured to encode the output from the first coder at a rate "within 10% of one."
  • The complaint does not explicitly reserve the right to assert other claims of the ’710 patent.

U.S. Patent No. 7,421,032 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

The Invention Explained

  • Problem Addressed: As with the related ’710 patent, this patent aims to provide a high-performance error correction code that avoids the implementation complexity of prior art turbo codes (’032 Patent, col. 1:36-43).
  • The Patented Solution: This patent claims the IRA code concept through a graphical representation known as a Tanner graph. The claimed graph structure defines the relationships between message bits ("variable nodes") and the resulting "parity bits." It specifies that message bits are repeated, with different subsets of bits being repeated a different number of times, and then connected through a "random permutation" to "check nodes" that enforce the mathematical constraints for generating the final encoded output (’032 Patent, Fig. 3; col. 3:28-51).
  • Technical Importance: Representing the code as a Tanner graph provides a framework for efficient, iterative decoding algorithms, which is a key reason for the strong performance of IRA codes (Compl. ¶23, ¶52).

Key Claims at a Glance

  • The complaint asserts at least claim 11 (Compl. ¶46).
  • Independent claim 11 is a device claim for an encoder that generates parity bits in accordance with a specific Tanner graph depicted in the claim itself. The key features of this graph, as described in the complaint, are:
    • Every message bit is repeated.
    • At least two different subsets of message bits are repeated a different number of times.
    • Check nodes are randomly connected to the repeated message bits.
    • These check nodes enforce constraints that determine the parity bits.
  • The complaint does not explicitly reserve the right to assert other claims of the ’032 patent.

U.S. Patent No. 7,716,552 - "Interleaved Serial Concatenation Forming Turbo-Like Codes"

  • Technology Synopsis: This patent is directed to "repeat and accumulate codes" (RA codes), a class of error correction codes related to the IRA codes of the other asserted patents (Compl. ¶20). The claimed system involves an outer encoder, an interleaver, and a specific type of inner encoder—a rate-1 convolutional code with a transfer function of 1/(1+D)—which functions as an accumulator (Compl. ¶66).
  • Asserted Claims: The complaint asserts at least claim 11 and also provides an infringement analysis for claim 8 (Compl. ¶¶ 60, 66).
  • Accused Features: The accused LDPC encoders in HP's products are alleged to contain an outer encoder, an interleaver subsystem, and an inner encoder that operate in a manner that meets the limitations of the asserted claims (Compl. ¶66).

U.S. Patent No. 7,916,781 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

  • Technology Synopsis: This patent claims a method of encoding a signal using IRA code principles. The core of the claimed method is an encoding operation that includes an "accumulation of mod-2 or exclusive-OR sums of bits in subsets of the information bits" (’781 Patent, claim 13).
  • Asserted Claims: The complaint asserts at least claim 13 (Compl. ¶73).
  • Accused Features: The encoding method performed by the LDPC encoders in HP products is accused. The complaint alleges that the summing of bits corresponding to the non-null values in the 802.11 standard's parity-check matrices constitutes the claimed accumulation operation (Compl. ¶79).

U.S. Patent No. 8,284,833 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

  • Technology Synopsis: This patent claims an apparatus for performing IRA encoding, focusing on the hardware structure. The claims describe a structure comprising distinct sets of memory locations for storing information bits and parity bits, a "permutation module" for reading and combining bits between these memory sets, and an "accumulator" for performing operations on the stored parity bits ('833 Patent, claim 1).
  • Asserted Claims: The complaint asserts at least claim 1 (Compl. ¶86).
  • Accused Features: The LDPC encoders in HP's products are alleged to be the infringing apparatus, containing the claimed sets of memory locations, permutation module, and accumulator (Compl. ¶92).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are a broad range of HP's Wi-Fi enabled products that are compliant with the IEEE 802.11n, 802.11ac, and/or 802.11ax standards. The complaint specifically lists product lines such as HP ProBook, EliteBook, Spectre, Envy, and Pavilion PCs, as well as LaserJet Pro and OfficeJet Pro wireless printers (Compl. ¶30).

Functionality and Market Context

The core accused functionality is the incorporation and use of LDPC (Low-Density Parity Check) encoders and decoders as specified by the 802.11 Wi-Fi standards (Compl. ¶30). The complaint alleges that these standard-compliant LDPC codes are, in fact, implementations of Caltech's patented IRA and RA code technology (Compl. ¶¶ 20, 26). The complaint posits that Wi-Fi usage is widespread in modern electronics, making the accused products part of a significant commercial market (Compl. ¶24). The complaint includes a table from the IEEE 802.11n standard, "Table 20-14—LDPC parameters," which defines the information and codeword block lengths for the 12 LDPC codes used in the standard (Compl. p. 8, ¶34). This table illustrates the specific standardized codes that are at the heart of the infringement allegations.

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,116,710 Infringement Allegations

Claim Element (from Independent Claim 15, as narrowed by Claim 20) Alleged Infringing Functionality Complaint Citation Patent Citation
A first coder operative to repeat said stream of bits irregularly and scramble the repeated bits The LDPC encoders in the accused products include first coders that correspond to the left-hand side of the 802.11 standard's parity-check matrices and are alleged to perform irregular repetition and scrambling. ¶38 col. 2:47-59
...wherein the first coder comprises a low-density generator matrix coder The left-hand side of the standard's parity-check matrices is allegedly structured in a way that corresponds to the use of a low-density generator matrix coder. ¶37, ¶38 col. 4:56-58
a second coder operative to further encode bits output from the first coder at a rate within 10% of one The LDPC encoders include second coders that correspond to the right-hand side of the parity-check matrices and allegedly perform accumulation, which is a form of encoding at a rate of one. ¶39 col. 2:59-64

Identified Points of Contention

  • Scope Questions: A central question may be whether the LDPC encoder defined in the 802.11 standard, specified by a single parity-check matrix, can be conceptually divided into the two distinct components required by claim 15: a "first coder" that is an LDGM coder and a separate "second coder" that is a rate-1 encoder. A defense may argue this is an artificial division of a single, integrated encoder structure.
  • Technical Questions: The complaint alleges that the structure of the standard's parity-check matrix "corresponds to the use of a low-density generator matrix" (Compl. ¶37). The case may turn on what level of technical correspondence is required to meet this limitation, and whether the accused encoders possess an actual LDGM coder or merely a structure that produces a mathematically similar result. The complaint provides "Table R.1—Matrix prototypes for codeword block length n=648 bits" as evidence of this structure (Compl. p. 9, ¶36).

U.S. Patent No. 7,421,032 Infringement Allegations

Claim Element (from Independent Claim 11) Alleged Infringing Functionality Complaint Citation Patent Citation
An encoder configured to ... encode ... in accordance with the following Tanner graph: The LDPC encoders in the Accused Products are alleged to encode message bits in accordance with a Tanner graph that can be constructed from the parity-check matrices in the 802.11 standard. ¶52, ¶53 col. 3:28-35
[A graph where] every message bit is repeated When constructing a Tanner graph from the 802.11 standard's parity-check matrices, message bits are repeated. ¶52, ¶53 col. 3:38-44
[A graph where] at least two different subsets of message bits are repeated a different number of times In the constructed Tanner graph for the 802.11 codes, different subsets of the information bits are repeated different numbers of times. ¶52, ¶53 col. 3:38-44
[A graph where] check nodes, randomly connected to the repeated message bits, enforce constraints In the constructed Tanner graph, check nodes are connected to information bits in a "random but known pattern" and enforce constraints to determine parity bits. ¶52, ¶53 col. 3:45-51

Identified Points of Contention

  • Scope Questions: Claim 11 is defined by the Tanner graph figure it contains. The dispute will likely focus on a direct, element-by-element comparison of that figure to the Tanner graph that represents the LDPC codes in the 802.11 standard. The key question is whether the 802.11 codes are properly classified as the specific type of "IRA code" embodied in the claim's graph.
  • Technical Questions: What evidence does the complaint provide that the connections in the 802.11 Tanner graph are "randomly connected" in the manner required by the claim? A defense could argue that the highly structured and deterministic nature of a standard-defined matrix does not constitute a "random" connection in the sense intended by the patent.

V. Key Claim Terms for Construction

Term (from ’710 Patent): "low-density generator matrix coder"

  • Context and Importance: This term is the central limitation of asserted claim 20. The infringement theory depends on whether the accused LDPC encoders, which are defined by parity-check matrices (H-matrices), can be characterized as this specific type of coder, which is typically defined by a generator matrix (G-matrix). Practitioners may focus on this term because the equivalence between an H-matrix representation and a G-matrix coder is a technical distinction that could be dispositive.
  • Intrinsic Evidence for a Broader Interpretation: The patent describes an LDGM coder as an alternative embodiment to an irregular repeater and interleaver, suggesting a functional rather than a strictly structural definition (’710 Patent, col. 4:52-58). This may support an interpretation where any encoder that performs the function of an LDGM coder infringes, regardless of its specific implementation.
  • Intrinsic Evidence for a Narrower Interpretation: The patent states, "As the name implies, an LDGM code has a sparse (low-density) generator matrix" (’710 Patent, col. 4:56-58). A party could argue this requires the physical or logical presence of an actual sparse generator matrix, not just an encoder whose function can be mathematically analogized to one.

Term (from ’032 Patent): The Tanner Graph of Claim 11

  • Context and Importance: The claim itself is dominated by a figure of a Tanner graph. The construction of this entire graphical limitation will be central, as infringement requires mapping the accused device directly onto it.
  • Intrinsic Evidence for a Broader Interpretation: The graph is depicted schematically, with elements like a box labeled "RANDOM PERMUTATION" (’032 Patent, Fig. 3). A party could argue this does not require a specific randomizing circuit, but rather any functional block that performs a pseudo-random permutation on the bit connections, which the fixed-but-complex mapping of the 802.11 standard could satisfy.
  • Intrinsic Evidence for a Narrower Interpretation: Because the claim is a picture claim, a party could argue that every depicted element—including the distinct separation of information nodes, the permutation block, check nodes, and parity nodes—must be found as a corresponding distinct structure in the accused device. The argument would be that the integrated nature of a standard LDPC encoder lacks this specific, partitioned graphical structure.

VI. Other Allegations

Indirect Infringement

The complaint exclusively asserts claims for direct infringement under 35 U.S.C. § 271(a) (e.g., Compl. ¶¶ 32, 46, 60) and does not contain allegations of indirect infringement (inducement or contributory infringement).

Willful Infringement

The complaint does not contain a separate count for willful infringement, but for each patent it alleges the infringement is "exceptional" and entitles Caltech to attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶ 44, 58, 71, 84, 97). The complaint establishes a potential basis for pre-suit knowledge by repeatedly referencing the prior, highly publicized $1.1 billion jury verdict Caltech obtained against Apple and Broadcom for infringement of several of the same patents, which may be used to argue that HP's post-verdict conduct was willful (Compl. ¶¶ 2, 27).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of definitional mapping: Can the LDPC encoders defined in the IEEE 802.11 standard, which are specified by unitary parity-check matrices, be legally and technically mapped onto the multi-component apparatus and method claims of the asserted patents? This raises the question of whether a single, integrated circuit structure can be said to contain the distinct "first coder" and "second coder" of the '710 patent or the separate memory and permutation modules of the '833 patent.
  • A key evidentiary question will be one of graphical equivalence: Does the Tanner graph corresponding to the 802.11 standard's LDPC codes embody the specific combination of irregular repetition, node degrees, and "random" connections depicted in claim 11 of the '032 patent, or is there a fundamental mismatch in their graphical structures?
  • A significant question regarding damages and fees will be the impact of prior litigation: To what extent can Caltech's prior successful verdict against major industry players on the same underlying technology be used to establish that HP had pre-suit knowledge of its infringement, potentially supporting a finding of willfulness or that this is an exceptional case?