DCT

6:20-cv-01211

Ocean Semiconductor LLC v. NVIDIA Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:20-cv-01211, W.D. Tex., 12/31/2020
  • Venue Allegations: Venue is alleged based on Defendant's regional office and regular and established place of business in Austin, Texas, within the district, where acts of infringement and product promotion events are alleged to have occurred.
  • Core Dispute: Plaintiff alleges that semiconductor products designed and sold by Defendant, and manufactured by third-party foundries using specific fabrication and process control systems, infringe nine patents related to semiconductor manufacturing processes, fault detection, scheduling, and integrated circuit packaging.
  • Technical Context: The technologies at issue concern foundational aspects of modern semiconductor manufacturing, including process control, fault detection, and physical packaging, which are critical for producing high-performance and high-yield integrated circuits such as graphics processing units (GPUs).
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendant with notice of infringement for the asserted patents on October 15, 2020, and November 25, 2020. Subsequent to the filing of this complaint, several of the asserted patents were challenged in inter partes review (IPR) proceedings before the Patent Trial and Appeal Board. The IPR certificates provided indicate that all claims of U.S. Patent Nos. 6,725,402, 6,907,305, 6,968,248, and 8,676,538 have since been cancelled, which may render the infringement counts related to those patents moot.

Case Timeline

Date Event
2000-07-31 Priority Date for U.S. Patent No. 6,725,402
2001-11-08 Priority Date for U.S. Patent No. 6,660,651
2002-04-30 Priority Date for U.S. Patent No. 6,907,305
2003-03-05 Priority Date for U.S. Patent No. 7,080,330
2003-05-01 Priority Date for U.S. Patent No. 6,836,691
2003-12-09 U.S. Patent No. 6,660,651 Issues
2004-04-20 U.S. Patent No. 6,725,402 Issues
2004-11-02 Priority Date for U.S. Patent No. 8,676,538
2004-12-28 U.S. Patent No. 6,836,691 Issues
2005-06-13 Priority Date for U.S. Patent No. 6,968,248
2005-06-14 U.S. Patent No. 6,907,305 Issues
2005-11-22 U.S. Patent No. 6,968,248 Issues
2006-07-18 U.S. Patent No. 7,080,330 Issues
2008-04-28 Priority Date for U.S. Patent No. 8,120,170
2012-02-01 Priority Date for U.S. Patent No. 8,847,383
2012-02-21 U.S. Patent No. 8,120,170 Issues
2014-03-18 U.S. Patent No. 8,676,538 Issues
2014-09-30 U.S. Patent No. 8,847,383 Issues
2016-05-06 NVIDIA announces GeForce GTX 1080 in Austin, TX
2020-10-15 Plaintiff provides notice of infringement for multiple patents
2020-11-25 Plaintiff provides notice of infringement for additional patents
2020-12-31 Complaint filed
2021-08-03 IPRs filed against ’402, ’305, ’248, and ’538 patents
2023-04-26 Certificate of Cancellation issues for U.S. Patent No. 6,968,248
2023-04-27 Certificate of Cancellation issues for U.S. Patent No. 8,676,538
2023-05-04 Certificate of Cancellation issues for U.S. Patent No. 6,907,305
2024-11-21 Certificate of Cancellation issues for U.S. Patent No. 6,725,402

II. Technology and Patent(s)-in-Suit Analysis

  • Patent Identification: U.S. Patent No. 6,660,651, Adjustable Wafer Stage, and a Method and System for Performing Process Operations Using Same, issued December 9, 2003.

  • The Invention Explained:

    • Problem Addressed: The patent addresses the technical problem of "across-wafer variations" in semiconductor manufacturing, where processes like deposition or etching produce non-uniform results (e.g., layers that are thicker at the wafer's edge than its center), which can negatively affect device performance and yield (’651 Patent, col. 2:35-51).
    • The Patented Solution: The invention proposes a process tool containing a wafer stage with a surface that can be physically raised, lowered, or tilted. By mechanically adjusting the plane of this stage, the system can compensate for known process non-uniformities during the processing of a wafer, thereby achieving a more uniform outcome. (’651 Patent, Abstract; col. 6:8-18).
    • Technical Importance: This technology provided a method for actively counteracting process non-uniformities within the fabrication tool itself, aiming to improve yield without requiring complex changes to the underlying chemical or plasma processes (Compl. ¶35).

  • Key Claims at a Glance:

    • The complaint asserts independent claim 19 (Compl. ¶83).
    • Essential elements of claim 19 include:
      • providing a process chamber with an adjustable wafer stage;
      • adjusting the wafer stage surface by actuating pneumatic cylinders to accomplish raising, lowering, and/or varying a tilt;
      • positioning a wafer on the stage; and
      • performing a process operation on the wafer.
    • The complaint reserves the right to assert other claims (Compl. ¶100).

  • Patent Identification: U.S. Patent No. 6,725,402, Method and Apparatus for Fault Detection of a Processing Tool and Control Thereof Using an Advanced Process Control (APC) Framework, issued April 20, 2004.

  • The Invention Explained:

    • Problem Addressed: The patent identifies the problem of delays in reporting manufacturing faults in semiconductor fabrication, which can result in the production of many faulty devices before a problem is identified and corrected, thereby increasing costs (Compl. ¶47; ’402 Patent, col. 1:30-37).
    • The Patented Solution: The invention discloses a method and system within an Advanced Process Control (APC) framework that receives operational state data from a processing tool. A fault detection unit analyzes this data to determine if a fault exists. If a fault is found, the system performs a "predetermined action" on the tool (e.g., shutting it down) and sends an alarm to the APC framework to prevent the creation of more defective products. (’402 Patent, Abstract; col. 7:45-58, Fig. 1).
    • Technical Importance: This invention describes a systematic, automated approach for near real-time fault detection and response in a fab, aiming to minimize the production of scrap and improve overall manufacturing yield (Compl. ¶47).

  • Key Claims at a Glance:

    • The complaint asserts independent claim 1 (Compl. ¶103).
    • Essential elements of claim 1 include:
      • receiving operational state data of a processing tool at a first interface;
      • sending the state data to a fault detection unit (via steps including accumulation and protocol translation at a data collection unit);
      • determining if a fault condition exists;
      • performing a predetermined action on the tool in response to a fault;
      • sending an alarm signal to an APC framework; and
      • sending a signal from the framework back to the first interface reflecting the action.
    • The complaint reserves the right to assert other claims (Compl. ¶120).

  • Multi-Patent Capsule: U.S. Patent No. 6,907,305

    • Patent Identification: U.S. Patent No. 6,907,305, Agent Reactive Scheduling in an Automated Manufacturing Environment, issued June 14, 2005 (Compl. ¶39).
    • Technology Synopsis: The patent addresses problems in factory control system utilization and scheduling. It describes a system using software "agents" that reactively schedule, initiate, and execute manufacturing activities (e.g., lot transport) in response to events occurring in the manufacturing process, such as a machine becoming available or a downtime occurrence, to optimize wafer throughput (Compl. ¶¶ 41, 43).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶123).
    • Accused Features: The manufacturing of NVIDIA products using systems like Applied Materials' SmartFactory and camLine's LineWorks, which are alleged to perform reactive scheduling in response to predetermined events in the process flow (Compl. ¶¶ 123, 126).

  • Multi-Patent Capsule: U.S. Patent No. 6,968,248

    • Patent Identification: U.S. Patent No. 6,968,248, Agent Reactive Scheduling in an Automated Manufacturing Environment, issued November 22, 2005 (Compl. ¶51).
    • Technology Synopsis: Similar to the ’305 Patent, this patent addresses technical problems in utilizing process tools and factory control systems. It describes agents that reactively schedule activities in response to factory state changes (e.g., a machine becoming available, a lot departing) to manage control systems and optimize wafer throughput (Compl. ¶¶ 53, 55).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶143).
    • Accused Features: The manufacturing of NVIDIA products using systems like Applied Materials' SmartFactory, alleged to automatically detect predetermined events and use a software scheduling agent to reactively schedule an action (Compl. ¶¶ 143, 146).

  • Multi-Patent Capsule: U.S. Patent No. 8,120,170

    • Patent Identification: U.S. Patent No. 8,120,170, Integrated Package Circuit with Stiffener, issued February 21, 2012 (Compl. ¶75).
    • Technology Synopsis: The patent addresses the problem of providing a thinner circuit board that still offers sufficient mechanical resistance for large-scale industrialization. The solution is an integrated circuit package that includes a substrate, a chip, a passive electronic component, and a "stiffener" with a bottom surface coupled to the substrate and having a space that at least partly surrounds the passive component (Compl. ¶77).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶163).
    • Accused Features: NVIDIA GPUs and graphics cards, such as the GeForce GTX 980M GPU, that are alleged to employ an integrated circuit package with the claimed stiffener structure (Compl. ¶¶ 20, 167).

  • Multi-Patent Capsule: U.S. Patent No. 8,847,383

    • Patent Identification: U.S. Patent No. 8,847,383, Integrated Circuit Package Strip with Stiffener, issued September 30, 2014 (Compl. ¶78).
    • Technology Synopsis: This patent also relates to providing thinner circuit boards with mechanical resistance. It describes an integrated circuit package strip comprising multiple integrated circuit packages, where at least one package has four lateral sections surrounding a stiffener, and at least two of these sections are shared with adjacent packages on the strip (Compl. ¶80).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶183).
    • Accused Features: NVIDIA GPUs and graphics cards, such as the GeForce GTX 1080Ti, that allegedly employ the claimed integrated circuit package strip structure (Compl. ¶¶ 22, 187).

  • Multi-Patent Capsule: U.S. Patent No. 7,080,330

    • Patent Identification: U.S. Patent No. 7,080,330, Concurrent Measurement of Critical Dimension and Overlay in Semiconductor Manufacturing, issued July 18, 2006 (Compl. ¶57).
    • Technology Synopsis: The patent addresses technical problems related to overlay errors in forming integrated circuits. It describes a method that monitors and controls a fabrication process by partitioning a wafer into grid blocks to facilitate concurrent measurements of critical dimensions and overlay, mitigating errors and achieving desired dimensions (Compl. ¶¶ 59, 61).
    • Asserted Claims: Independent claim 19 is asserted (Compl. ¶203).
    • Accused Features: The manufacturing of NVIDIA products using ASML's YieldStar metrology and inspection system, which is alleged to perform the claimed method of concurrent measurement of critical dimensions and overlay on wafers mapped into logical grids (Compl. ¶¶ 203, 207).

  • Multi-Patent Capsule: U.S. Patent No. 6,836,691

    • Patent Identification: U.S. Patent No. 6,836,691, Method and Apparatus for Filtering Metrology Data Based on Collection Purpose, issued December 28, 2004 (Compl. ¶63).
    • Technology Synopsis: The patent addresses the problem of process controllers collecting metrology data that does not accurately reflect the state of the fabrication process. It describes a method of generating "context data" (including "collection purpose" data) for metrology data and then filtering that data to remove outliers, thereby improving the performance of the process controller (Compl. ¶65).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶224).
    • Accused Features: The manufacturing of NVIDIA products using Applied Materials' E3 system and PDF Solutions' Exensio system, which are alleged to collect metrology data, collect context data including collection purpose data, and filter the metrology data based on that purpose (Compl. ¶¶ 224, 227).

  • Multi-Patent Capsule: U.S. Patent No. 8,676,538

    • Patent Identification: U.S. Patent No. 8,676,538, Adjusting Weighting of a parameter Relating to Fault Detection Based on a Detected Fault, issued March 18, 2014 (Compl. ¶69).
    • Technology Synopsis: This patent addresses problems related to inaccurately detecting faults in manufacturing. It describes a method for using a dynamic weighting technique in fault detection analysis, which involves determining a relationship of a parameter to a detected fault and adjusting a weighting associated with that parameter based on the relationship (Compl. ¶71).
    • Asserted Claims: Independent claim 1 is asserted (Compl. ¶244).
    • Accused Features: The manufacturing of NVIDIA products using Applied Materials' E3 and PDF Solutions' Exensio systems, which are alleged to perform fault detection analysis where a relationship of a parameter to a detected fault is determined and a weighting of that parameter is adjusted based on the relationship (Compl. ¶¶ 244, 247).

III. The Accused Instrumentality

  • Product Identification: The complaint targets NVIDIA's semiconductor products, including but not limited to its GeForce, TITAN, SHIELD, Jetson, and QUADRO product lines ("Accused Products") (Compl. ¶¶ 7, 11, 14). However, the infringement allegations are primarily directed at the third-party manufacturing systems and processes used by NVIDIA's foundry partners (e.g., UMC and TSMC) to fabricate these products (Compl. ¶8). These accused systems include fabrication equipment from ASML (the TWINSCAN system), process control frameworks from Applied Materials (the E3 system and SmartFactory) and PDF Solutions (the Exensio system), and metrology systems from ASML (the YieldStar system) (Compl. ¶¶ 9, 10, 13, 16, 18).
  • Functionality and Market Context: The complaint alleges that NVIDIA, through its contractual relationships with foundry partners, uses these third-party systems to design, develop, and manufacture its semiconductor devices for importation into and sale in the United States (Compl. ¶¶ 8, 11). The resulting NVIDIA products are commercially significant components in the communications, internet of things, automotive, computer, and consumer electronics industries (Compl. ¶7). The accused manufacturing systems represent industry-standard platforms for advanced semiconductor fabrication and process control (Compl. ¶¶ 9-19).

IV. Analysis of Infringement Allegations

The complaint references claim-chart exhibits that are not provided; therefore, the infringement theories are summarized below in prose.

  • U.S. Patent No. 6,660,651 Infringement Allegations
    The complaint alleges that NVIDIA's products are manufactured by a process that infringes at least claim 19 of the ’651 Patent (Compl. ¶83). This process is allegedly carried out by NVIDIA's foundry partners using manufacturing systems such as the ASML TWINSCAN system (Compl. ¶83). The complaint asserts that during this manufacturing process, a wafer stage with an adjustable surface is provided, and this surface is adjusted by "raising, lowering, and varying a tilt." Following this adjustment, a wafer is positioned on the stage and a process operation is performed (Compl. ¶86).

  • U.S. Patent No. 6,725,402 Infringement Allegations
    The complaint alleges that NVIDIA's products are manufactured by a process that infringes at least claim 1 of the ’402 Patent (Compl. ¶103). This process allegedly utilizes systems such as the Applied Materials E3 system and/or PDF Solutions' Exensio system (Compl. ¶103). The complaint's narrative alleges that these systems perform each step of the claimed method: receiving "operational state data" from a processing tool at a "first interface," sending this data to a "data collection unit" where it is accumulated and translated, and then sending it to a "fault detection unit." This unit then determines if a fault exists, which prompts a "predetermined action" on the tool and an alarm signal to an "advanced process control framework" (Compl. ¶106).

  • Identified Points of Contention:

    • Technical Questions for '651 Patent: A central question may be whether the accused ASML TWINSCAN system's wafer stage performs the specific function of compensating for "cross-wafer variations" as taught by the patent (’651 Patent, col. 2:35-51). The complaint alleges the physical movements of raising, lowering, and tilting (Compl. ¶86), but it does not provide specific facts linking these movements to the patented purpose of correcting for process non-uniformities.
    • Scope Questions for '651 Patent: The analysis may turn on whether routine wafer leveling or positioning in the accused systems constitutes "adjusting" in the manner claimed. The scope of "adjusting...to accomplish at least one of raising, lowering and varying a tilt" will be a key issue for claim construction.
    • Technical Questions for '402 Patent: A key factual question will be how the commercial architecture of the accused Applied Materials and PDF Solutions systems maps onto the specific multi-unit structure recited in claim 1 (e.g., "first interface," "data collection unit," "fault detection unit"). The complaint alleges a direct mapping, but the actual implementation may present mismatches (Compl. ¶106).
    • Evidentiary Questions for '402 Patent: The complaint alleges that a "predetermined action is performed" in response to a fault but does not specify what that action is (Compl. ¶106). Establishing the existence and nature of this responsive action within the accused third-party systems will be an evidentiary hurdle.

V. Key Claim Terms for Construction

  • For the '651 Patent (Claim 19):

    • The Term: "adjusting said surface of said wafer stage"
    • Context and Importance: The infringement case for this patent hinges on whether routine movements of the wafer stage in the accused ASML TWINSCAN system meet this limitation. Practitioners may focus on this term because the dispute will likely distinguish between general-purpose wafer positioning and the specific, corrective adjustments taught in the patent's specification.
    • Intrinsic Evidence for a Broader Interpretation: The plain language of claim 19 recites the physical acts of "raising, lowering and varying a tilt" without an explicit statement of purpose within the claim itself (’651 Patent, col. 11:2-12).
    • Intrinsic Evidence for a Narrower Interpretation: The patent specification, including the "Summary of the Invention" and "Detailed Description," consistently describes the purpose of the adjustment as compensating for "across-wafer variations" produced by the process operation (’651 Patent, col. 2:52-65; col. 6:8-18). A court may be persuaded to import this purpose into the construction of "adjusting."

  • For the '402 Patent (Claim 1):

    • The Term: "fault detection unit"
    • Context and Importance: This term defines a core structural component of the claimed method. Its construction will be critical because the accused systems are complex commercial software platforms where fault detection functions may be distributed across multiple modules rather than residing in a single, discrete "unit."
    • Intrinsic Evidence for a Broader Interpretation: The patent's block diagram depicts the "FAULT DETECTION SYSTEM" as a distinct block (120), but the specification describes its function in terms of what it does—determining "if a fault condition exists" (’402 Patent, Fig. 1; Abstract). This functional description could support a construction that covers a set of logically associated software components that collectively perform the task.
    • Intrinsic Evidence for a Narrower Interpretation: The use of the term "unit" and its depiction as a standalone block in Figure 1 could support an argument that the claim requires a more structurally distinct component, not merely a distributed function within a larger software framework (’402 Patent, Fig. 1).

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement of infringement for all asserted patents. The factual basis for these allegations is that Defendant actively encourages its foundry partners to use the allegedly infringing manufacturing systems and instructs its customers on the use of the resulting products through technical specifications, marketing materials, developer tools, and customer support (Compl. ¶¶ 89-90, 109-110).
  • Willful Infringement: Willfulness is alleged for all asserted patents. The allegations are based on Defendant's alleged actual knowledge of the patents and their infringement since at least October 15, 2020, and November 25, 2020, the dates on which Plaintiff claims to have provided notice to Defendant (Compl. ¶¶ 99, 102, 119, 122).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A primary issue will be one of viability and validity: given that all asserted claims of four of the nine patents-in-suit have been cancelled in subsequent IPR proceedings, can the claims of the remaining five patents withstand the likely invalidity challenges that will be based on similar arguments and prior art?
  • A central evidentiary question will be one of third-party proof: since the infringement allegations target complex and proprietary manufacturing systems operated by non-parties (e.g., TSMC, UMC), what evidence can Plaintiff obtain to prove that these systems actually perform every step of the asserted method claims in the manner required?
  • A key technical question will be one of functional equivalence vs. inherent capability: does the evidence show that the accused manufacturing systems are specifically operated to achieve the patented solutions (e.g., tilting a wafer stage for the purpose of correcting process non-uniformities), or do they merely possess general capabilities (e.g., an adjustable stage for wafer handling) that Plaintiff alleges reads on the claims?