DCT
6:21-cv-00061
Liberty Patents LLC v. Lattice Semiconductor Corp
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Liberty Patents, LLC (Texas)
- Defendant: Lattice Semiconductor Corporation (Delaware)
- Plaintiff’s Counsel: Antonelli, Harrington & Thompson LLP; The Stafford Davis Firm
- Case Identification: 6:21-cv-00061, W.D. Tex., 01/22/2021
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendant has committed acts of patent infringement in the district and maintains a regular and established place of business in Austin, Texas.
- Core Dispute: Plaintiff alleges that Defendant’s programmable clock generator integrated circuits, specifically the ispClock family, infringe two patents related to zero-delay buffer (ZDB) technology for synchronizing multiple clock signals.
- Technical Context: The technology addresses the critical need for precise timing synchronization across multiple outputs in high-speed semiconductor devices, a fundamental challenge in modern electronics like FPGAs and communication systems.
- Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of the patents-in-suit. Specifically, it states that the parent '530 Patent was cited by the U.S. Patent and Trademark Office against a patent application assigned to Defendant in 2005. This allegation may form the basis for a claim of willful infringement.
Case Timeline
| Date | Event |
|---|---|
| 2001-12-14 | Priority Date for '530 Patent and '740 Patent |
| 2003-08-19 | Issue Date for U.S. Patent No. 6,608,530 |
| 2004-05-11 | Issue Date for U.S. Patent No. 6,734,740 |
| 2005-02-25 | Alleged pre-suit knowledge date ('530 Patent cited against Lattice) |
| 2008-06-01 | Launch Date for Accused ispClock 5600A Family |
| 2021-01-22 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,608,530 - "Enhanced ZDB Feedback Methodology Utilizing Binary Weighted Techniques"
- Patent Identification: U.S. Patent No. 6,608,530, "Enhanced ZDB Feedback Methodology Utilizing Binary Weighted Techniques," issued August 19, 2003.
The Invention Explained
- Problem Addressed: In conventional Zero Delay Buffer (ZDB) circuits with multiple clock outputs, typically only one output is part of a "closed-loop" feedback system, while the remaining outputs operate in an "open-loop" mode. These open-loop outputs are susceptible to parametric variations (e.g., temperature, voltage, loading effects) that can cause undesirable timing differences, or skew, between the various clock signals (’530 Patent, col. 2:4-16, 56-65).
- The Patented Solution: The invention introduces a system where any of the multiple output clock signals can be selected to serve as the feedback signal for the phase-locked loop (PLL). This is achieved using a selection circuit, such as a multiplexer, which is controlled by a programmable state machine. By allowing multiple or all outputs to participate in the feedback process over time, the system can approximate a fully closed-loop circuit, thereby minimizing delay differences and improving synchronization across all outputs (’530 Patent, Abstract; col. 5:6-18; Fig. 3).
- Technical Importance: This architecture provided a method to enhance the robustness and timing precision of clock distribution networks in complex integrated circuits without the cost and complexity of implementing multiple, separate PLLs for each output channel (Compl. ¶9).
Key Claims at a Glance
- The complaint asserts independent claim 1 and dependent claim 15 (Compl. ¶16).
- Independent Claim 1:
- An apparatus comprising:
- a first circuit configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal; and
- a second circuit configured to select one of said plurality of output clock signals as said feedback signal in response to a first control signal,
- wherein said first control signal is configured to minimize a difference in delay between said plurality of output clock signals.
U.S. Patent No. 6,734,740 - "Enhanced ZDB Feedback Methodology Utilizing Binary Weighted Techniques"
- Patent Identification: U.S. Patent No. 6,734,740, "Enhanced ZDB Feedback Methodology Utilizing Binary Weighted Techniques," issued May 11, 2004.
The Invention Explained
- Problem Addressed: As a continuation of the application leading to the ’530 Patent, this patent addresses the same technical problem: timing skew among multiple open-loop clock outputs in a ZDB circuit due to parametric variations (’740 Patent, col. 2:4-16, 56-65).
- The Patented Solution: The invention describes a similar apparatus but with a distinct claim structure. It claims a "first circuit" that generates both the plurality of output clock signals and a control signal. A "second circuit" then uses this control signal to select one of the outputs as the feedback signal (’740 Patent, Abstract; col. 4:5-16). This architecture creates a tightly coupled system where the clock generation and feedback selection are explicitly linked by a control signal originating from the same primary circuit.
- Technical Importance: This approach likewise aimed to create a more predictable and synchronized clock distribution system, critical for the reliable operation of high-performance semiconductor devices (Compl. ¶9).
Key Claims at a Glance
- The complaint asserts independent claim 1 and dependent claim 16 (Compl. ¶36).
- Independent Claim 1:
- An apparatus comprising:
- a first circuit configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal; and
- a second circuit configured to select one of said plurality of output clock signals as said feedback signal in response to said first control signal.
III. The Accused Instrumentality
Product Identification
- The complaint accuses Lattice’s ispClock 5600A Family devices and other products incorporating ZDB technology (Compl. ¶15, ¶35).
Functionality and Market Context
- The accused products are identified as "In-System Programmable, Enhanced Zero-Delay Clock Generator[s]" used in high-performance communications and computing applications (Compl. ¶18, ¶24). A block diagram from the accused product's datasheet illustrates a Phase Locked Loop (PLL) core, multiple output dividers, and an internal feedback path (Compl. p. 10). The product datasheet highlights features such as "Low Output to Output Skew (<50ps)" and a "Flexible Clock Reference and External Feedback Inputs" system that includes a "Feedback A/B selection multiplexer" (Compl. p. 6).
- The complaint alleges the products support an "Internal Feedback Mode," which allows for the selection of one of the internal clock signals to be routed back as the feedback signal, a central element of the infringement allegations (Compl. ¶19, ¶26). Text from the datasheet explains that "Loop feedback may be taken internally from the output of any of the five V-dividers" (Compl. p. 11).
- The complaint positions Defendant as a "global leader in smart connectivity solutions" and the "world's largest volume supplier of FPGAs," suggesting the commercial importance of the accused technology (Compl. ¶3).
IV. Analysis of Infringement Allegations
'530 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first circuit configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal; | The accused devices' PLL, divider circuits, voltage-controlled oscillator (VCO), and output drivers allegedly form a "first circuit" that generates multiple clock outputs based on a reference input and a feedback input. | ¶18 | col. 8:35-49 |
| and a second circuit configured to select one of said plurality of output clock signals as said feedback signal in response to a first control signal, | The accused devices allegedly contain circuitry, including an "Internal/External Feedback Select" multiplexer, that selects one of the multiple clock outputs to serve as the internal feedback signal based on a control signal. | ¶19, ¶21 | col. 9:42-51 |
| wherein said first control signal is configured to minimize a difference in delay between said plurality of output clock signals. | The complaint alleges that the control signal, by enabling a closed-loop configuration for the selected output, is inherently configured to minimize delay and achieve the advertised "low output-to-output skew." | ¶21, ¶22 | col. 3:15-18 |
'740 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first circuit configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal; | The complaint alleges that the accused devices' PLL and associated logic (VCO, dividers, drivers) constitute the "first circuit" that generates both the clock outputs and the control signal used for feedback selection. | ¶38, ¶39, ¶42 | col. 5:11-24; col. 5:52-66 |
| and a second circuit configured to select one of said plurality of output clock signals as said feedback signal in response to said first control signal. | The accused devices' feedback selection circuitry allegedly operates in response to the control signal generated by the "first circuit" to select one of the clock outputs as the feedback signal. | ¶40, ¶42 | col. 5:42-51 |
- Identified Points of Contention:
- Scope Questions: A central question for the ’530 Patent is the interpretation of "minimize a difference in delay." The dispute may focus on whether this requires an active, dynamic process of adjusting for skew across all outputs, or if the inherent delay reduction achieved by selecting any single output for a closed-loop feedback path is sufficient to meet the limitation.
- Technical Questions: For the ’740 Patent, a key question is whether a single "first circuit" generates both the clock signals and the control signal, as required by the claim. A defendant may argue that the patent’s own diagrams show the PLL and the control logic as distinct circuits, potentially creating a structural mismatch with the claim language.
V. Key Claim Terms for Construction
Term 1 (from '530 Patent): "minimize a difference in delay"
- Context and Importance: The interpretation of this functional language is critical. Infringement depends on whether the accused device's feedback selection mechanism, which is guided by a control signal, performs this specific function.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent states that feedback "mitigates external effects and ensures high predictability and accuracy," which could support an argument that any closed-loop feedback system inherently "minimizes" delay differences compared to an open-loop alternative (’530 Patent, col. 2:28-34).
- Evidence for a Narrower Interpretation: The specification discloses advanced schemes such as "round-robin" and "binary weighting" to select the feedback signal, which "may generate an integration best fit response" (’530 Patent, col. 5:50-col. 6:23). This may support an argument that "minimize" requires a more sophisticated, dynamic process than merely locking to a single, statically chosen output.
Term 2 (from '740 Patent): "a first circuit"
- Context and Importance: The claim requires this single "first circuit" to generate both clock signals and a control signal. The entire claim structure depends on this antecedent basis. Practitioners may focus on this term because a narrow construction could defeat the infringement allegation on structural grounds.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party could argue that "circuit" should be interpreted functionally to mean the entire clock generation subsystem on the integrated circuit, which would encompass both the PLL core and the associated control logic as a single functional unit.
- Evidence for a Narrower Interpretation: The patent’s own block diagram (Fig. 3) depicts the PLL (112) and the "Programmable State Control" (118) as separate, interconnected blocks. This could support a narrow construction where the PLL that generates the clock signals is a distinct circuit from the control logic that generates the control signal, meaning no single "first circuit" performs both claimed functions.
VI. Other Allegations
- Indirect Infringement: The complaint alleges both induced and contributory infringement. Inducement is based on allegations that Defendant advises customers and provides instructions (e.g., datasheets) on using the products in an infringing manner (Compl. ¶56-57). Contributory infringement is based on the allegation that the circuitry for reducing clock delay constitutes a special feature that is a material part of the invention and is not a staple article of commerce suitable for substantial non-infringing use (Compl. ¶72-74).
- Willful Infringement: The complaint alleges that Defendant had pre-suit knowledge of the patents, specifically citing a February 25, 2005 office action in which the ’530 Patent was cited by a USPTO examiner against a patent application assigned to Defendant (Compl. ¶30, ¶51). The complaint further alleges that Defendant's actions were "objectively reckless" and that it maintains a policy of being "willfully blind" to the patent rights of others (Compl. ¶78-79).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of claim construction: for the ’740 Patent, can the term "a first circuit" be construed to cover both the PLL core and its separate control logic as a single entity, as the plaintiff's theory appears to require, or do the patent’s own diagrams compel a narrower definition that would present a significant hurdle to proving infringement?
- A second central question will be one of functional scope: for the ’530 Patent, does the act of selecting a single output for feedback inherently satisfy the requirement to "minimize a difference in delay," or does the claim demand a more dynamic, responsive system that actively manages skew across multiple outputs, as suggested by the specification's more advanced embodiments?
- A key evidentiary matter will surround willfulness: given the allegation of pre-suit knowledge dating back to a 2005 patent prosecution file, the case may turn on what evidence can be marshaled to establish that Defendant's subsequent conduct met the legal standard for objective recklessness.