DCT
6:21-cv-00259
Super Interconnect Techonologies LLC v. Google LLC
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Super Interconnect Technologies LLC (Texas)
- Defendant: Google LLC (Delaware)
- Plaintiff’s Counsel: Bragalone Olejko Saad PC; Ward, Smith & Hill, PLLC
- Case Identification: 6:21-cv-00259, W.D. Tex., 03/15/2021
- Venue Allegations: Plaintiff alleges venue is proper because Google has committed acts of infringement in the district and maintains a regular and established place of business in Austin, Texas.
- Core Dispute: Plaintiff alleges that Defendant’s Google Pixel smartphone series, which incorporates Universal Flash Storage (UFS), infringes three patents related to high-speed serial data transmission and signaling techniques.
- Technical Context: The technology at issue involves methods for efficiently transmitting clock, data, and control signals over a single serial communication link, a critical function for connecting processors and storage in power-constrained mobile devices.
- Key Procedural History: The complaint alleges that Google was put on notice of its infringement of all three patents-in-suit during prior litigation between the parties, Super Interconnect Techs. LLC v. Google LLC, No. 2:18-cv-00463 (E.D. Tex.). This prior notice, which allegedly included a detailed expert report on infringement, forms the basis for the willfulness allegations in the current case.
Case Timeline
| Date | Event |
|---|---|
| 1998-09-10 | '092 Patent Priority Date |
| 2001-03-16 | '593 Patent Priority Date |
| 2002-10-08 | '092 Patent Issue Date |
| 2005-10-31 | '044 Patent Priority Date |
| 2007-01-02 | '593 Patent Issue Date |
| 2009-12-01 | '044 Patent Issue Date |
| 2016-10-04 | Accused Product (Google Pixel) launch alleged |
| 2018 | Notice alleged via prior litigation in E.D. Tex. |
| 2021-03-15 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,627,044 - "Clock-Edge Modulated Serial Link with DC-Balance Control," issued Dec. 1, 2009
The Invention Explained
- Problem Addressed: The patent describes the challenge of designing low-power interfaces for mobile devices, noting that conventional parallel interfaces with separate lines for clock, data, and control signals consume excessive power, space, and create electromagnetic radiation (’044 Patent, col. 1:11-34).
- The Patented Solution: The invention proposes a single-channel serial link that transmits clock, data, and control information simultaneously. This is achieved by using pulse-width modulation (PWM), where the position of a clock edge (e.g., the falling edge) is varied to encode data, while the other edge (e.g., the rising edge) remains periodic for clock recovery (’044 Patent, Abstract). Critically, the system incorporates direct current (DC) balancing control signals into the PWM scheme to maintain signal integrity over the channel, for instance by choosing between a shorter (e.g., 25%) or longer (e.g., 75%) duty cycle to encode a bit based on the running DC value of previously transmitted bits (’044 Patent, col. 3:20-43).
- Technical Importance: This approach reduces the physical pin count and hardware complexity in mobile electronics, which directly contributes to lower power consumption and smaller device form factors (’044 Patent, col. 2:19-24).
Key Claims at a Glance
- The complaint asserts independent claim 1 and dependent claims 2, 8-15, and 19 (Compl. ¶¶ 12-13).
- Independent Claim 1 recites:
- A signal transmitter, comprising:
- a channel node to interface with a single direct current balanced differential channel;
- circuitry connected to the channel node, the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node;
- wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals.
U.S. Patent No. 6,463,092 - "System and Method for Sending and Receiving Data Signals Over A Clock Signal Line," issued Oct. 8, 2002
The Invention Explained
- Problem Addressed: The patent identifies inefficiencies in prior art data communication systems that use separate lines for clock and data signals, which limits available bandwidth and can introduce latency when sending control signals. It also notes the lack of a simple mechanism for a receiver to communicate back to a transmitter without adding costly hardware (’092 Patent, col. 1:24-63).
- The Patented Solution: The invention describes a system that embeds data within the clock signal itself on a single transmission line. It achieves this by modulating the position of the clock signal’s falling edge to represent data values, while preserving the periodic rising edge for clock recovery at the receiver (’092 Patent, Abstract; col. 4:27-36). The patent also discloses a method for the receiver to superimpose return signals onto the same line, enabling bi-directional communication (’092 Patent, col. 2:37-45).
- Technical Importance: This technique maximizes bandwidth on a single channel, reduces hardware complexity and pin count, and provides for a low-latency return channel, all of which are valuable in designing integrated circuits (’092 Patent, col. 2:1-4).
Key Claims at a Glance
- The complaint asserts independent claim 1 and dependent claims 2, 5, 10, and 11 (Compl. ¶¶ 28-29).
- Independent Claim 1 recites:
- An apparatus for transmitting a clock signal and data signals over a signal line, the apparatus comprising:
- a clock generator having a first input, a second input and an output;
- the clock generator modulating a falling edge of an output signal to indicate different data values;
- the first input of the clock generator coupled to receive a clock signal; and
- the second input of the clock generator coupled to receive a control signal indicating a data value to be transmitted.
Multi-Patent Capsule
- Patent Identification: U.S. Patent No. 7,158,593, "Combining a Clock Signal and a Data Signal," issued Jan. 2, 2007.
- Technology Synopsis: The patent discloses a method for combining clock and data signals for transmission on a single channel, particularly in high-frequency systems where jitter can degrade performance. The solution involves using an encoding scheme that shifts the energy spectrum of the data signal to a higher frequency, away from the effective loop bandwidth of the receiver’s clock recovery circuit. This allows the receiver’s phase-locked loop (PLL) to more easily filter out the data-related noise and recover a cleaner clock signal. (’593 Patent, Abstract; col. 2:62-67).
- Asserted Claims: The complaint asserts independent claim 34 and dependent claim 35 (Compl. ¶¶ 44-45).
- Accused Features: The complaint alleges that transmitters in the accused products generate a combined clock and encoded data signal where the encoding scheme shifts the signal’s energy spectrum away from the clock recovery block’s effective loop bandwidth (Compl. ¶49).
III. The Accused Instrumentality
- Product Identification: The Google Pixel and Google Pixel XL series of smartphones (Compl. ¶¶ 12, 28, 44).
- Functionality and Market Context: The complaint alleges that the accused smartphones incorporate Universal Flash Storage (UFS) and that the physical layer for communication between the UFS host and the UFS device utilizes the MIPI M-PHY protocol (Compl. ¶¶ 15-16). A diagram included in the complaint illustrates this architecture, showing the M-PHY block as the physical interface connecting the UFS host and device. (Compl. p. 5, Fig. 2). A text excerpt also cited in the complaint states that the UFS specification uses M-PHY Type 1, which employs both NRZ and PWM signaling (Compl. p. 5, M-PHY I/O). Plaintiff alleges the UFS technology is a key feature, citing a third-party article that praises the Pixel's "Fast storage (UFS 2.0)" and positions the device as a competitor to the iPhone (Compl. ¶15).
IV. Analysis of Infringement Allegations
'044 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a channel node to interface with a single direct current balanced differential channel | The UFS hosts and devices in the accused products contain signal transmitters that drive DC-balanced differential signals (e.g., Dout+/-, Din+/-) for a communications channel. The complaint provides a diagram showing this interface. | ¶17, p. 5 | col. 3:4-7 |
| circuitry connected to the channel node | The transmitters in the accused products include circuitry that connects to the communications channel node. | ¶17 | col. 3:52-56 |
| the circuitry being configured to multiplex clock, data and control signals and apply them to the channel node | The transmitters allegedly include circuitry that multiplexes clock, data, and control signals and applies them to the communications channel node, allowing UFS hosts and devices to communicate. | ¶17 | col. 3:52-56 |
| wherein the clock signal is pulse width modulated to incorporate direct current balancing control signals | The complaint alleges the accused products incorporate the technologies of the ’044 patent and notes that the M-PHY standard used by UFS employs "PWM signaling for LS [low-speed]." The complaint concludes that the products meet all limitations. | ¶¶12, 17, 18, p. 5 | col. 3:15-19 |
- Identified Points of Contention:
- Technical Question: The central dispute will likely concern the final element of claim 1. The complaint alleges the accused products use PWM signaling but provides limited factual support connecting that signaling to the claim’s specific requirement that it be used to "incorporate direct current balancing control signals." The case may turn on technical evidence demonstrating whether the M-PHY protocol’s PWM mode performs this exact function or if its DC-balancing is achieved through other means.
'092 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a clock generator having a first input, a second input and an output | The accused products are alleged to include a clock generator with multiple inputs. | ¶33 | col. 4:25-26 |
| the clock generator modulating a falling edge of an output signal to indicate different data values | The clock generator allegedly modulates the falling edge of an output signal to indicate different data values, enabling data transmission between UFS components. | ¶33 | col. 4:29-34 |
| the first input of the clock generator coupled to receive a clock signal | The complaint alleges the products transmit a "clock and data signal over a signal line," implying the clock generator receives a clock input. | ¶33 | col. 4:43-47 |
| the second input...coupled to receive a control signal indicating a data value to be transmitted | The complaint alleges that at least one of the inputs to the clock generator is a "control signal indicating a data value to be transmitted." | ¶33 | col. 4:47-49 |
- Identified Points of Contention:
- Scope Question: A key issue will be whether the signaling method of the MIPI M-PHY standard falls within the scope of "modulating a falling edge" as that phrase is used in the patent. The infringement analysis will depend on a detailed technical comparison between how M-PHY signaling works and the specific mechanisms described and claimed in the ’092 patent.
V. Key Claim Terms for Construction
Term from the ’044 Patent: "direct current balancing control signals"
- Context and Importance: This term is the core of the asserted claim's novelty. The infringement analysis will hinge on whether the signals transmitted in the accused M-PHY system constitute "control signals" for DC balancing that are actively "incorporate[d]" via PWM, or if the system's DC balance is merely an inherent property of a different type of line code.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the concept generally, stating that the choice between a 25% and 75% duty cycle pulse is "determined by the DC value of the bits transmitted so far" (’044 Patent, col. 3:32-34). This could support a broad reading covering any PWM scheme where pulse width is adjusted to maintain DC balance.
- Evidence for a Narrower Interpretation: The patent’s specific embodiment describes a distinct control scheme where a special sequence of symbols (e.g., two consecutive "1+" pulses) indicates that the following symbols represent control characters (’044 Patent, col. 3:45-53). A defendant may argue that a "control signal" must be an explicit, discrete signal of this nature, rather than an implicit adjustment.
Term from the ’092 Patent: "modulating a falling edge of an output signal"
- Context and Importance: This phrase defines the fundamental data encoding mechanism of the asserted claim. The dispute will turn on whether the operation of the accused M-PHY protocol can be properly characterized as this specific type of modulation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes the invention as varying "the modulation of the falling edge of the clock signal" while preserving the rising edge for clock recovery (’092 Patent, col. 4:29-36). This could be argued to encompass any signaling scheme where the time between a periodic rising edge and a variable falling edge encodes data.
- Evidence for a Narrower Interpretation: The detailed description and figures show a specific implementation where a delay-locked loop and a multiplexer are used to select one of several discrete, phase-shifted signals to generate the falling edge (’092 Patent, Fig. 3; col. 6:3-16). A party could argue the term should be limited to this specific architecture of selecting from predefined phases.
VI. Other Allegations
- Indirect Infringement: The complaint alleges Google induces infringement by third-party manufacturers and end-users. The alleged inducing acts include creating advertisements, establishing distribution channels, and providing instruction manuals and technical support for the accused Pixel smartphones (Compl. ¶¶ 22, 38, 54).
- Willful Infringement: The complaint alleges willful infringement of all three patents. The primary basis for this allegation is pre-suit knowledge stemming from prior litigation between the parties, in which Plaintiff claims it "repeatedly and explicitly set forth Google's infringement... including in a detailed expert report" (Compl. ¶¶ 20, 36, 52). The complaint further alleges that Google continued to release new products incorporating the accused technology (e.g., Pixel 5 and 4a) after receiving this notice (Compl. ¶¶ 20, 36, 52).
VII. Analyst’s Conclusion: Key Questions for the Case
This case appears to center on two main areas of dispute that will require significant factual and expert evidence to resolve.
- A primary issue will be one of technical-factual mapping: Do the signaling protocols defined in the MIPI M-PHY standard, as used in Google's UFS implementation, actually practice the specific methods claimed by the patents? This will require a granular analysis of whether M-PHY signaling involves "incorporat[ing] direct current balancing control signals" via PWM (’044 patent) or "modulating a falling edge" (’092 patent) in the manner the patents define.
- A second key question will be one of intent and damages: Given the strong allegations of pre-suit notice via detailed infringement contentions in a prior lawsuit, a central issue for trial will be whether Google’s conduct rises to the level of willful infringement. The resolution of this question will be critical, as a finding of willfulness could expose Google to a potential award of enhanced damages.