California Institute Of Technology v. Microsoft Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: The California Institute of Technology (Caltech) (California)
  • Defendant: Microsoft Corporation (Washington)
  • Plaintiff’s Counsel: Quinn Emanuel Urquhart & Sullivan, LLP; Mann Tindel Thompson
• Case Identification: 6:21-cv-00276, W.D. Tex., 07/14/2021
• Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains corporate offices in the district, and a substantial part of the events giving rise to the infringement claims occurred there.
• Core Dispute: Plaintiff alleges that Defendant’s Wi-Fi-enabled products, including its Surface and Xbox lines, infringe four patents related to efficient error-correction coding technology.
• Technical Context: The patents concern Irregular Repeat-Accumulate (IRA) codes, a type of forward error correction technology designed to enable reliable data transmission over noisy channels, such as Wi-Fi, at rates approaching the theoretical maximum (the "Shannon limit").
• Key Procedural History: The complaint highlights that three of the four asserted patents (’710, ’032, and ’781) were previously found to be infringed by Apple and Broadcom, resulting in a jury verdict for Caltech exceeding $1.1 billion. Additionally, the complaint notes that all four asserted patents survived ten inter partes review (IPR) challenges filed by Apple, where the Patent Trial and Appeal Board (PTAB) either denied institution or upheld the patentability of the challenged claims. This history suggests the patents have previously withstood significant validity and infringement scrutiny. All asserted patents expired on August 18, 2020, limiting any potential remedy to past damages.

Case Timeline

Date	Event
2000-05-18	Earliest Priority Date for '710, '032, '781, and ’833 Patents
2000-09-01	Inventors publish paper on "Irregular Repeat-Accumulate Codes"
2006-10-03	'710 Patent Issued
2008-09-02	'032 Patent Issued
2009-01-01	IEEE 802.11n standard, incorporating LDPC codes, is referenced
2011-03-29	'781 Patent Issued
2012-10-09	'833 Patent Issued
2013-01-01	IEEE 802.11ac standard (basis for Wi-Fi 5) finalized
2016-05-01	Caltech files suit against Apple and Broadcom
2020-01-29	Jury verdict in Caltech v. Broadcom
2020-08-18	Asserted Patents Expire
2021-07-14	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,116,710 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

The Invention Explained

• Problem Addressed: Prior art error-correcting codes, such as "turbo codes," were effective at allowing reliable communication near a channel's capacity but involved relatively complex encoding and decoding algorithms ('710 Patent, col. 1:21-34).
• The Patented Solution: The invention proposes a more efficient coding system constructed from two main components: an "outer coder" and an "inner coder" (Compl. ¶18; '710 Patent, Fig. 2). The outer coder first processes a block of data by "irregularly" repeating the bits—meaning different bits are repeated a different number of times—and then scrambling them with an interleaver. This output is then fed to an "inner coder," which is a simple, rate-1 "accumulator" that performs a running sum operation ('710 Patent, col. 2:35-65).
• Technical Importance: This "Irregular Repeat and Accumulate" (IRA) structure provided a novel way to construct powerful error-correction codes that achieve performance comparable to more complex turbo codes but with simpler, more efficient circuitry (Compl. ¶18-19).

Key Claims at a Glance

• The complaint asserts at least independent claim 20 (Compl. ¶30).
• Claim 20 of the '710 Patent requires:
  • A coder for encoding a signal, comprising:
  • a first coder which is a low-density generator matrix coder; and
  • a second coder operative to further encode bits output from the first coder, wherein the second coder comprises a rate 1 linear encoder.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,421,032 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

The Invention Explained

• Problem Addressed: Similar to the '710 patent, this patent addresses the need for powerful but computationally simple error-correction codes ('032 Patent, col. 1:30-43).
• The Patented Solution: The '032 patent describes the IRA code invention through the lens of a "Tanner graph," a graphical representation of the code's structure ('032 Patent, col. 3:30-35). The claimed encoder operates according to a Tanner graph with specific properties: every message bit is repeated, different subsets of message bits are repeated a different number of times, and "check nodes" are randomly connected to the repeated message bits to enforce parity constraints ('032 Patent, Claim 11). This graphical structure defines the irregular repetition and accumulation process.
• Technical Importance: Representing the code as a Tanner graph provides a framework for both efficient encoding and a low-complexity iterative decoding scheme, contributing to the practical advantages of IRA codes (Compl. ¶21, ¶50).

Key Claims at a Glance

• The complaint asserts at least independent claim 11 (Compl. ¶44).
• Claim 11 of the '032 Patent requires:
  • A device comprising an encoder configured to receive a collection of message bits and encode them to generate parity bits in accordance with a specific "Tanner graph."
  • The Tanner graph itself is a limitation, defined by having message bit nodes, parity bit nodes, and check nodes, where:
    • every message bit is repeated,
    • at least two different subsets of message bits are repeated a different number of times, and
    • check nodes are randomly connected to the repeated message bits and enforce constraints that determine the parity bits.
• The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,916,781 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

• Patent Identification: U.S. Patent No. 7,916,781, "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes," Issued March 29, 2011.
• Technology Synopsis: The '781 patent claims a method of encoding that involves an "accumulation of mod-2 or exclusive-OR sums of bits in subsets of the information bits" ('781 Patent, Claim 13; Compl. ¶64). This describes the generation of transformed bits from information bits using a process that mirrors the structure of a low-density generator matrix, which are then subject to an accumulation process. The technology is another facet of the IRA code family.
• Asserted Claims: At least independent claim 13 (Compl. ¶58).
• Accused Features: The LDPC encoders in the Accused Products, which allegedly receive a block of information bits and perform an encoding operation that includes an accumulation of sums of bits in subsets of the information bits, corresponding to the structure of the parity-check matrices in the 802.11 standards (Compl. ¶64).

U.S. Patent No. 8,284,833 - "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes"

• Patent Identification: U.S. Patent No. 8,284,833, "Serial Concatenation of Interleaved Convolutional Codes Forming Turbo-Like Codes," Issued October 9, 2012.
• Technology Synopsis: The '833 patent claims an apparatus for performing encoding, focusing on the hardware structure. It requires a first set of memory locations for information bits, a second set for parity bits, a "permutation module" that combines bits from the first set into the second set, and an "accumulator" for the parity bits ('833 Patent, Claim 1). This apparatus is structured to perform irregular repetition, where different memory locations for information bits are read a different number of times.
• Asserted Claims: At least independent claim 1 (Compl. ¶71).
• Accused Features: The LDPC encoders in the Accused Products, which are alleged to be an apparatus with memory locations, a permutation module, and an accumulator that together implement the claimed encoding operations (Compl. ¶77).

III. The Accused Instrumentality

Product Identification

• Microsoft's Wi-Fi enabled products, including but not limited to the Surface family (e.g., Surface Book, Surface Go, Surface Pro) and Xbox products (Compl. ¶28).

Functionality and Market Context

• The relevant functionality of the Accused Products is their inclusion of Wi-Fi components that comply with the IEEE 802.11n, 802.11ac, and/or 802.11ax standards (Compl. ¶28). A key technical aspect of these standards is their use of Low-Density Parity-Check (LDPC) codes for error correction (Compl. ¶24). The complaint alleges that the LDPC encoders within the Accused Products implement the 12 specific LDPC codes defined in the 802.11n standard (and carried forward in subsequent standards) by using Caltech's patented IRA code technology (Compl. ¶24, ¶31, ¶33). The complaint presents a table from the IEEE standard listing the parameters for these 12 LDPC codes, including various coding rates and block lengths (Compl. ¶32, Table 20-14). The complaint alleges that implementations infringing the patents are more efficient in terms of computations, memory, power, and die area (Compl. ¶31).

IV. Analysis of Infringement Allegations

'710 Patent Infringement Allegations

Claim Element (from Independent Claim 20)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first coder which is a low-density generator matrix coder	The LDPC encoders in the Accused Products include "first coders" that are low-density generator matrix coders. This functionality corresponds to the left-hand side of the parity-check matrices defined in the 802.11 standard, which dictates irregular repetition and scrambling of information bits. A visual example of such a matrix is provided in the complaint. (Table R.1, Compl. ¶34-35).	¶36	col. 2:47-56
a second coder operative to further encode bits output from the first coder, wherein the second coder comprises a rate 1 linear encoder	The LDPC encoders include "second coders" that encode the output from the first coders at a rate within 10% of one. This functionality corresponds to the accumulation process depicted in the right-hand side of the 802.11 standard's parity-check matrices.	¶37	col. 2:59-65

'032 Patent Infringement Allegations

Claim Element (from Independent Claim 11)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an encoder configured to...encode the message bits to generate a collection of parity bits in accordance with the following Tanner graph	The LDPC encoders in the Accused Products allegedly encode message bits in accordance with the claimed Tanner graph. The complaint alleges that the structure of the 12 LDPC codes in the 802.11 standard is such that a Tanner graph constructed from their parity-check matrices exhibits the properties of the claimed graph.	¶51	col. 3:30-50
wherein...every message bit is repeated, at least two different subsets of message bits are repeated a different number of times	The complaint alleges that when constructing a Tanner graph from the 12 LDPC parity-check matrices in the 802.11 standard, "message bits are repeated, [and] different subsets of the information bits are repeated different numbers of times," matching this claim element.	¶50-51	col. 3:41-43

Identified Points of Contention

• Technical Equivalence: A central technical question will be whether the LDPC codes specified in the IEEE 802.11 standards are, in fact, implementations of the patented IRA codes. The defense may argue that while both are types of LDPC codes, the specific structures and operations mandated by the standard are technically distinct from the architectures recited in the patent claims.
• Architectural Mapping: For the '710 patent, a point of contention may be whether the accused LDPC encoders can be fairly characterized as having the discrete "first coder" (for irregular repetition/scrambling) and "second coder" (for accumulation) as claimed, or if they employ a different, more integrated architecture.
• Structural Scope: For the '032 patent, the dispute will likely focus on whether the parity-check matrices for the 802.11 LDPC codes, when represented as a Tanner graph, meet every structural limitation of claim 11, including the requirements for how "check nodes, [are] randomly connected to the repeated message bits."

V. Key Claim Terms for Construction

Term ('710 Patent): "low-density generator matrix coder"

• Context and Importance: This term from claim 20 defines the nature of the "first coder." Plaintiff's infringement theory equates this with the functionality implied by the left-hand side of the 802.11 parity-check matrix (Compl. ¶36). Practitioners may focus on this term because its construction will determine if the accused standard-compliant encoders, which are defined by parity-check matrices, can be said to be the claimed "generator matrix coder."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes this component functionally as performing an "irregular repeat of the k bits" ('710 Patent, col. 3:51-54), which could support a construction not strictly tied to a specific matrix implementation.
  • Evidence for a Narrower Interpretation: The term itself, "low-density generator matrix," is a specific term of art in coding theory. A defendant may argue that the specification's detailed discussion of Tanner graphs and degree profiles ('710 Patent, col. 3:25-4:65) limits the term to a particular structure that is not present in the accused devices.

Term ('032 Patent): "Tanner graph"

• Context and Importance: The entirety of asserted claim 11 is defined by the structure of a "Tanner graph." The infringement case for this patent rests on mapping the 802.11 LDPC codes onto this claimed graphical structure (Compl. ¶50-51). The definition of the graph, particularly the nature of its connections, is therefore critical.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 11 itself provides a list of required characteristics for the graph (e.g., "every message bit is repeated," "at least two different subsets...are repeated a different number of times"). A party could argue that any graph meeting these functional descriptions is covered.
  • Evidence for a Narrower Interpretation: The specification provides a detailed visual example in Figure 3 and an accompanying description ('032 Patent, col. 3:30-50), which could be used to argue that the term implies specific structural features shown in that embodiment, such as the clear separation between information nodes and parity nodes.

VI. Other Allegations

Indirect Infringement

• The complaint focuses on direct infringement under 35 U.S.C. § 271(a), alleging that Microsoft "manufactures, uses, imports, offers for sale, and/or sells" the Accused Products (Compl. ¶28, ¶30). The complaint does not plead specific facts to support claims for induced or contributory infringement.

Willful Infringement

• The complaint does not include a specific count for willful infringement. However, for each asserted patent, it alleges that Microsoft's infringement is "exceptional" and seeks attorneys' fees pursuant to 35 U.S.C. § 285 (e.g., Compl. ¶42, ¶56). The basis for this allegation is not explicitly stated, but may be inferred from the extensive public history of the patents, including the high-profile litigation against Apple and Broadcom and the multiple IPR proceedings.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of standards-to-patent mapping: Does compliance with the IEEE 802.11n/ac/ax standards, which mandate the use of specific LDPC codes, necessarily result in infringement of the asserted patent claims? The case will likely require a detailed technical comparison between the architecture defined by the standards' parity-check matrices and the specific claim limitations of the IRA code patents.
• A second key question will be one of claim construction and scope: Given the patents' successful navigation of prior litigation and IPRs, the dispute may focus heavily on claim construction. The viability of the infringement case will depend on whether the court construes terms like "low-density generator matrix coder" and the structural elements of the "Tanner graph" broadly enough to read on the accused standards-compliant products.
• Finally, a central damages question will be one of apportionment and royalty base: Since the asserted patents cover only the Wi-Fi error-correction component (the LDPC encoder) within complex, multi-feature products like the Surface and Xbox, a key battleground will be determining the appropriate royalty base and the value attributable to the patented technology, especially in light of the prior $1.1 billion award against different parties.