DCT
6:21-cv-00487
Vervain LLC v. Micron Technology Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Vervain, LLC (Texas)
- Defendant: Micron Technology, Inc. (Delaware); Micron Semiconductor Products, Inc. (Idaho); Micron Technology Texas, LLC (Idaho)
- Plaintiff’s Counsel: McKool Smith, P.C.
- Case Identification: 6:21-cv-00487, W.D. Tex., 05/10/2021
- Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Defendants maintain "regular and established places of business" in the district, including offices in Austin, Texas, where they employ engineering and sales staff and own property.
- Core Dispute: Plaintiff alleges that Defendant’s solid-state drive (SSD) products infringe four patents related to methods for managing hybrid non-volatile memory systems that combine Multi-Level Cell (MLC) and Single-Level Cell (SLC) flash memory to improve device lifetime.
- Technical Context: The technology addresses the trade-off between high-capacity, lower-cost, and lower-endurance MLC flash and lower-capacity, higher-cost, and higher-endurance SLC flash, a central design challenge in the SSD market.
- Key Procedural History: The asserted patents originate from the same family of applications. The complaint provides extensive background on the sole inventor, Dr. G.R. Mohan Rao, a veteran of the semiconductor industry, but does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2011-07-19 | Earliest Priority Date for all Asserted Patents |
| 2014-11-18 | U.S. Patent No. 8,891,298 Issues |
| 2015-11-24 | U.S. Patent No. 9,196,385 Issues |
| 2018-06-12 | U.S. Patent No. 9,997,240 Issues |
| 2021-03-16 | U.S. Patent No. 10,950,300 Issues |
| 2021-05-10 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,891,298 - “Lifetime Mixed Level Non-Volatile Memory System”
The Invention Explained
- Problem Addressed: The patent's background describes the inherent conflict in flash memory design between lower-cost, high-density Multi-Level Cell (MLC) memory, which has limited write endurance, and more expensive, lower-density Single-Level Cell (SLC) memory, which has significantly higher endurance (’298 Patent, col. 3:36-52).
- The Patented Solution: The invention proposes a memory system with both MLC and SLC modules managed by a controller. The controller improves the system's overall lifetime by implementing specific management rules: it remaps data from an MLC block to a higher-endurance SLC block if a data integrity test fails, and it allocates frequently written data to the SLC module to prevent premature wear on the MLC module (’298 Patent, Abstract; col. 5:5-14). Figure 2B of the patent illustrates the remapping of a logical address range from a failed MLC block to a new SLC block (’298 Patent, Fig. 2B).
- Technical Importance: This hybrid management approach allows storage devices to achieve high capacity and lower cost by using MLC for the bulk of storage, while strategically using SLC to handle high-wear data and reliability issues, thereby extending the useful life of the entire device (’298 Patent, col. 4:4-9).
Key Claims at a Glance
- Independent claim 1 is asserted (Compl. ¶57).
- Essential elements of claim 1 include:
- A system with at least one MLC non-volatile memory module and at least one SLC non-volatile memory module.
- A controller coupled to the modules.
- The controller is adapted to:
- (a) maintain an address map from logical to physical addresses in either the MLC or SLC module.
- (b) determine if a write to an MLC address range fails a data integrity test and, if so, remap that address to an SLC module.
- (c) determine the most frequently accessed blocks by maintaining access counts.
- (d) allocate the most frequently written blocks by transferring their contents to the SLC module.
- The complaint reserves the right to assert additional claims (Compl. ¶58).
U.S. Patent No. 9,196,385 - “Lifetime Mixed Level Non-Volatile Memory System”
The Invention Explained
- Problem Addressed: The patent addresses the same technical problem as the ’298 Patent: managing different types of flash memory to optimize for both cost and endurance (’385 Patent, col. 3:5-15, col. 4:45-54).
- The Patented Solution: This patent frames the solution more specifically around a "flash translation layer" (FTL), a standard architectural component in modern SSDs. The FTL itself is claimed as being adapted to perform the data management tasks: maintaining the address map, remapping blocks from MLC to SLC upon a data integrity failure, and allocating blocks based on write frequency (’385 Patent, Abstract; col. 8:50-54). The patent's Figure 4 depicts the FTL managing both MLC (60a, 60b) and SLC (62a, 62b) memory banks (’385 Patent, Fig. 4).
- Technical Importance: By situating the inventive logic within the FTL, the patent provides a more concrete and industry-aligned implementation of the hybrid memory management concept, moving from a generic "controller" to a specific, recognized software/firmware layer in SSD architecture (’385 Patent, col. 8:50-54).
Key Claims at a Glance
- Independent claim 1 is asserted (Compl. ¶71).
- Essential elements of claim 1 include:
- A system with at least one MLC and at least one SLC non-volatile memory module.
- A flash translation layer (FTL).
- The FTL is adapted to perform the same four functions (a-d) as the controller in claim 1 of the ’298 patent.
- The complaint reserves the right to assert additional claims (Compl. ¶72).
U.S. Patent No. 9,997,240 - “Lifetime Mixed Level Non-Volatile Memory System”
- Technology Synopsis: This patent refines the logic for managing frequently accessed data. It describes a controller that maintains a count value for frequently accessed blocks and, upon reaching a "predetermined count value," transfers the contents of those blocks to the SLC memory module. This adds a specific triggering mechanism for data migration (’240 Patent, Abstract; col. 8:51-68).
- Asserted Claims: Independent claim 6 is asserted (Compl. ¶85).
- Accused Features: The complaint alleges that Micron's wear-leveling techniques, which employ block erase counting and transfer blocks within flash memory, meet these claim limitations (Compl. ¶¶91, 93).
U.S. Patent No. 10,950,300 - “Lifetime Mixed Level Non-Volatile Memory System”
- Technology Synopsis: This patent explicitly adds "random access volatile memory" (e.g., DRAM) to the claimed system. It describes a controller that uses this volatile memory to perform a data integrity test by retaining a copy of data written to an MLC element and then comparing it to the data stored in the MLC element. A failure of this test triggers the remapping to SLC memory to achieve "enhanced endurance" (’300 Patent, Abstract; col. 8:1-12).
- Asserted Claims: Independent claim 1 is asserted (Compl. ¶98).
- Accused Features: The complaint alleges that the accused SSDs contain DRAM memory space and that the controller performs data integrity tests by comparing data stored in flash memory with data retained in the DRAM (Compl. ¶¶101, 105, 108).
III. The Accused Instrumentality
Product Identification
- The complaint identifies certain Micron flash memory products, including the M600 SATA SSD, 2200 SSD, 2210 SSD, and 2300 SSD, with the M600 being the primary exemplary product (Compl. ¶51).
Functionality and Market Context
- The accused SSDs are alleged to utilize a hybrid memory architecture. A key feature cited is "Dynamic Write Acceleration," where the drive's firmware can switch NAND blocks between SLC and MLC modes on-the-fly. This creates a "high-speed SLC pool that changes in size and location with usage conditions" to accelerate write performance (Compl. ¶61). A visual from a Micron datasheet describes this adaptive usage of the SSD's native NAND array (Compl. p. 16).
- The complaint alleges the SSDs contain a controller that manages a logical-to-physical address mapping table (referred to as an "L2P Table") to track data locations (Compl. ¶63). A diagram from a product datasheet illustrates this L2P table, which is stored in DRAM (Compl. p. 19).
- The products are alleged to incorporate "advanced technology for defect and error management," including hardware-based error correction and firmware-based wear-leveling algorithms, to manage data integrity and increase the lifetime of the NAND flash (Compl. ¶¶64, 78, 92).
IV. Analysis of Infringement Allegations
8,891,298 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A system for storing data comprising: at least one MLC non-volatile memory module...; at least one SLC non-volatile memory module... | The accused M600 SSD contains MLC NAND flash technology and is also configured to operate in an SLC mode, with the controller switching between modes on-the-fly to create a high-speed SLC pool. | ¶¶60-61 | col. 4:55-60 |
| a controller coupled to the at least one MLC non-volatile memory module and the at least one SLC non-volatile memory module | The M600 SSD contains a controller that is coupled to the NAND memory array, which operates in both MLC and SLC modes. A functional block diagram from the M600 datasheet shows the SSD controller connected to the NAND memory. | ¶62; p.15 | col. 5:15-18 |
| a) maintain an address map...wherein each entry...maps to a similar range of physical addresses within either the at least one SLC...or...MLC non-volatile memory module; | The M600 controller uses a mapping table (L2P Table) to track the relationship between logical blocks and physical addresses. The "Dynamic Write Acceleration" feature maps data to either the SLC pool or the main MLC array. | ¶63 | col. 5:1-5 |
| b) determine if a range of addresses...fails a data integrity test, and, in the event of such a failure, the controller remaps the entry to the next available equivalent range of physical addresses within the at least one SLC...module; | The M600 incorporates "defect and error management technology." The complaint cites a technical note explaining that COPYBACK operations can detect and correct data errors, and alleges the controller addresses integrity issues by remapping data. | ¶64 | col. 5:5-14 |
| c) determine which of the blocks...are accessed most frequently by maintaining a count of the number of times each one of the blocks is accessed; and | The M600 employs wear-leveling techniques that use block erase counting. A Micron technical note explains the controller tracks erase counts to manage block wear. | ¶65; p. 23 | col. 6:24-28 |
| d) allocate those blocks that receive the most frequent writes by transferring the respective contents of those blocks to the at least one SLC non-volatile memory module. | The M600 employs wear-leveling techniques that transfer blocks within the flash memory to evenly distribute wear. Data is written to the high-speed SLC pool to handle write bursts. | ¶66 | col. 6:29-35 |
9,196,385 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A system for storing data comprising...at least one MLC...module; at least one SLC...module; a flash translation layer (FTL); | The M600 SSD contains MLC and SLC flash technology and includes a Flash Translation Layer (FTL), as described in a Micron technical note on wear leveling. | ¶¶74-76 | col. 8:50-54 |
| wherein the FTL is adapted to: a) maintain an address map... | The FTL in the M600 uses a mapping table (L2P Table) to track the relationship between logical blocks and physical addresses in the flash memory, which includes both SLC and MLC portions. | ¶77 | col. 4:1-9 |
| b) determine if a range of addresses...fails a data integrity test, and...the controller remaps the entry to the next available...range of physical addresses within the at least one SLC...module; | The M600 FTL incorporates defect and error management technology and addresses data integrity issues by remapping data. The complaint cites documents on wear leveling and COPYBACK operations to support this. | ¶78 | col. 4:10-18 |
| c) determine which of the blocks...are accessed most frequently by maintaining a count...; and d) allocate those blocks that receive the most frequent writes... | The M600 FTL employs wear-leveling techniques that use block erase counting to determine access frequency and transfers blocks within the flash memory to manage wear and handle write-intensive operations. | ¶¶79-80 | col. 4:19-30 |
Identified Points of Contention
- Scope Questions: A primary question will concern the interpretation of "at least one MLC...module" and "at least one SLC...module." The complaint alleges infringement by Micron's "Dynamic Write Acceleration," where the same physical NAND array is operated in either SLC or MLC mode (Compl. ¶61). This raises the question of whether a single, dynamically partitioned memory array can satisfy the claim requirement for two distinct types of "modules," or if the claims require physically separate SLC and MLC components.
- Technical Questions: The complaint alleges that the accused products' "defect and error management technology" performs the claimed "data integrity test" (Compl. ¶64). A key technical question will be what evidence demonstrates that this general error management function is the same as the specific remapping scheme recited in the claims. The analysis may depend on whether Micron's standard ECC or other error handling mechanisms trigger a remapping from MLC to an SLC-mode block in the specific manner claimed.
V. Key Claim Terms for Construction
The Term: "non-volatile memory module"
- Context and Importance: This term appears in the preamble of the independent claims of the lead patents (e.g., ’298 Patent, cl. 1). Its construction is critical because the claims require "at least one MLC...module" and "at least one SLC...module." Practitioners may focus on this term because the accused products allegedly use a single, unified NAND array where blocks are dynamically configured into SLC or MLC modes, rather than using physically separate chips for each type. The outcome of this construction could determine whether the accused architecture falls within the scope of the claims.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claims use the general term "module," and the specification does not explicitly define it as requiring separate physical devices. One could argue a "module" can be a logical partition within a larger physical component, which would support finding infringement.
- Evidence for a Narrower Interpretation: The patent figures, such as Figure 4 of the ’385 Patent, depict MLC and SLC memory as distinct banks (e.g., 60a/60b and 62a/62b), which could be argued to imply physically separate structures. The repeated use of "at least one" for each type could also suggest they are distinct entities.
The Term: "data integrity test"
- Context and Importance: This term is central to the data remapping function in the independent claims (e.g., ’298 Patent, cl. 1(b)). Its definition will determine what kind of error-checking mechanism infringes. Practitioners may focus on this term to distinguish the patented method from conventional error correction codes (ECC) common in all SSDs. If the term is construed narrowly to require a specific process (e.g., a read-after-write comparison), it may be more difficult for the plaintiff to prove infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term is not explicitly defined, which may support a plain and ordinary meaning that encompasses any test that verifies the correctness of stored data, including standard ECC.
- Evidence for a Narrower Interpretation: The specification of the related ’300 Patent describes a specific implementation where the controller performs the test "by comparing the stored data to the retained data in the random access volatile memory" after a write operation (’300 Patent, col. 8:1-6). This specific embodiment could be used to argue for a narrower construction that excludes other forms of error detection.
VI. Other Allegations
- Indirect Infringement: The complaint does not contain allegations of indirect infringement.
- Willful Infringement: The complaint does not allege willful infringement. It does request that the case be found "exceptional" under 35 U.S.C. § 285 to recover attorneys' fees, but it does not plead the pre- or post-suit knowledge required for a willfulness claim (Compl. ¶¶69, 83, 96, 113).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the claim term "non-volatile memory module" be construed to read on a single, unified NAND flash array that is dynamically partitioned by firmware into logical SLC and MLC modes, as allegedly implemented in Micron's "Dynamic Write Acceleration" feature? The case may turn on whether the patents require physically distinct components or if logical partitioning is sufficient.
- A key evidentiary question will be one of functional operation: does the accused SSDs' general "defect and error management" and wear-leveling algorithms perform the specific, multi-step data management functions as recited by the claims? The dispute will likely focus on whether Micron's technology, upon detecting a data error, triggers the specific "remapping" to an SLC-mode block as claimed, or if it employs a technically distinct method of error correction and block retirement that falls outside the patent's scope.