DCT
6:22-cv-00066
InnoMemory LLC v. Procore Tech Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: InnoMemory, LLC (Texas)
- Defendant: Procore Technologies, Inc. (Delaware)
- Plaintiff’s Counsel: Ni, Wang & Massand, PLLC
- Case Identification: 6:22-cv-00066, W.D. Tex., 01/18/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant has committed acts of infringement in the district and maintains a regular and established place of business in Austin, Texas.
- Core Dispute: Plaintiff alleges that Defendant’s use of computing devices running its software, where such devices contain LPDDR3-compliant memory, infringes a patent related to methods for reducing power consumption during memory refresh operations.
- Technical Context: The technology at issue involves power-saving techniques for dynamic random-access memory (DRAM), a critical component in battery-powered electronics where standby power consumption affects device longevity.
- Key Procedural History: The complaint alleges that Defendant received notice of a different patent owned by Plaintiff, U.S. Patent 8,826,394, in August 2021, which may be used to support allegations of knowledge or willfulness regarding infringement.
Case Timeline
| Date | Event |
|---|---|
| 2002-03-04 | ’960 Patent Priority Date |
| 2006-06-06 | ’960 Patent Issued |
| 2021-08-01 | Defendant allegedly received notice of a related patent |
| 2022-01-18 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,057,960 - METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS
- Patent Identification: U.S. Patent No. 7,057,960, issued June 6, 2006.
The Invention Explained
- Problem Addressed: The patent describes that conventional dynamic semiconductor memory devices refresh all memory cells even when in a standby or low-power mode, consuming significant current. This is inefficient for battery-powered portable devices where only a portion of the memory may contain data that needs to be retained (’960 Patent, col. 1:36-52).
- The Patented Solution: The invention proposes a method and architecture that divides a memory array into multiple sections and selectively controls "background operations," such as refresh, on a section-by-section basis. By activating the support circuitry only for the sections being refreshed and leaving the others inactive, the device can significantly reduce power consumption during standby (’960 Patent, Abstract; col. 2:36-55). This selective control is achieved through control signals generated in response to a programmable address signal that designates which memory sections to refresh (’960 Patent, col. 4:56-65).
- Technical Importance: This approach provided a more granular method of power management for memory, addressing a key demand in the growing mobile device market for components with lower power standby modes (’960 Patent, col. 1:31-35).
Key Claims at a Glance
- The complaint asserts independent claim 1 (’960 Patent, Compl. ¶10).
- The essential elements of Claim 1 are:
- A method for reducing power consumption during background operations in a memory array with multiple sections.
- Controlling the background operations in each section in response to one or more control signals.
- The control signals are generated in response to a programmable address signal.
- The background operations can be enabled simultaneously and independently in two or more sections.
- Presenting the control signals and decoded address signals to the periphery array circuits of the sections.
III. The Accused Instrumentality
Product Identification
- The "Accused Product" is identified as Procore's software and Android application when used on computing devices that contain memory compliant with the LPDDR specification, with the Asus ZenPad 3S with LPDDR3 memory cited as an example (Compl. ¶9).
Functionality and Market Context
- The complaint alleges that the accused devices incorporate LPDDR3 RAM based on the JEDEC industry standard (Compl. ¶11). This standard allegedly includes a "Partial Array Self Refresh" (PASR) feature, which allows the device to limit refresh operations to selected memory banks by programming mode registers MR16 and MR17. The complaint alleges that using devices with this functionality to run Procore software, including for internal testing, constitutes performance of the patented method (Compl. ¶10-12). The complaint does not provide detail on the market context of the accused software beyond its use by Defendant's customers. No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’960 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method for reducing power consumption during background operations in a memory array with a plurality of sections... | The accused LPDDR3 RAM works in a "Self-Refresh Mode" which enables a refresh operation ("background operation") in selected memory banks ("plurality of sections") of a RAM memory ("memory array") (Compl. ¶11). | ¶11 | col. 2:36-39 |
| controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals... | The bits in the MR16 and MR17 mode registers are used to control the sections of the memory array on which the Self Refresh operation is enabled or disabled. These programmed bits allegedly function as the "control signals" (Compl. ¶12). | ¶12 | col. 4:46-50 |
| wherein said one or more control signals are generated in response to a programmable address signal... | The bits in the MR16 and MR17 registers are programmed to '0' (unmasked) or '1' (masked), which the complaint alleges constitutes a "programmable address signal" that controls the refresh operation (Compl. ¶12). | ¶12 | col. 4:56-65 |
| and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section... | The Partial Array Self Refresh (PASR) Bank Mask settings allegedly enable the refresh operation for unmasked banks while blocking it for masked banks, allowing for independent control of different memory sections (Compl. ¶12). | ¶12 | col. 4:3-13 |
| and presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections. | The LPDDR3 RAM allegedly has periphery array circuits (e.g., Column Decoders, Row Decoders) that receive control and address signals to provide access to the memory banks (Compl. ¶13). | ¶13 | col. 2:41-44 |
- Identified Points of Contention:
- Scope Questions: The complaint alleges that Procore "uses" devices that perform the patented method (Compl. ¶11). A central question will be whether running software on a device is legally sufficient to constitute "performing" or "controlling" a low-level hardware method that is an integral part of an industry-standard component. This raises the question of whether the allegedly infringing actor is the defendant, the hardware manufacturer, the OS provider, or the end user.
- Technical Questions: The infringement theory equates programming bits in a mode register (MR16/MR17) with the claimed "programmable address signal" (Compl. ¶12). The litigation may focus on whether this interpretation is technically and legally sound, or if the claim term requires a more specific structure, such as the "refresh address register" (138) that receives a "refresh block address" as disclosed in the patent's embodiment (’960 Patent, Fig. 3).
V. Key Claim Terms for Construction
The Term: "programmable address signal"
- Context and Importance: The infringement case hinges on whether programming mode register bits in standard LPDDR3 memory meets this limitation. Plaintiff’s theory depends on a broad construction, while Defendant will likely argue for a narrower definition tied to the patent's specific disclosure.
- Intrinsic Evidence for a Broader Interpretation: The claim term itself is not explicitly defined in the patent. Plaintiff may argue that any programmable input that results in the selection of memory sections for a background operation falls within the plain and ordinary meaning of the term.
- Intrinsic Evidence for a Narrower Interpretation: The patent’s preferred embodiment discloses a specific "refresh address register" (138) that is loaded with a "refresh block address" (AR1) to generate signals that control which blocks are refreshed (’960 Patent, Fig. 3; col. 4:56-65). A party could argue that this disclosure limits the term to an explicit address-based selection mechanism, rather than the configuration-bit approach used in the accused LPDDR3 standard.
The Term: "controlling said background operations"
- Context and Importance: Practitioners may focus on this term because Plaintiff alleges that Defendant, a software provider, is "controlling" a hardware-level function. The interpretation of "controlling" will be critical to determining direct infringement liability.
- Intrinsic Evidence for a Broader Interpretation: The patent does not define "controlling." Plaintiff may argue that by causing a device to enter a low-power state through the operation of its software, Defendant is effectively "controlling" the resultant power-saving method for its benefit, for example during internal testing (Compl. ¶10).
- Intrinsic Evidence for a Narrower Interpretation: The patent’s disclosed embodiments show a dedicated "refresh control" circuit (134) that responds to a "REF_CMD" signal to manage the refresh process (’960 Patent, Fig. 3). A party could argue that "controlling" requires this type of direct, command-level management of the hardware, which is typically handled by a device’s operating system or firmware, not a high-level application.
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Defendant induces infringement by its end-user customers (Compl. ¶15). The factual basis for inducement includes providing the Accused Product and posting support articles, such as one advising customers on which tablet devices to purchase for using Procore's software (Compl. ¶17).
- Willful Infringement: The complaint does not use the term "willful," but it does allege that Defendant's induced infringement is "exceptional" and entitles Plaintiff to attorney fees under 35 U.S.C. § 285 (Compl. ¶19). This claim is supported by allegations that Defendant has known of the infringement since at least the filing of the complaint and was on notice of Plaintiff's patent portfolio due to correspondence regarding a related patent in August 2021 (Compl. ¶16).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of agency and control: Does a software company's use of a third-party device for running its application constitute "controlling" a low-level hardware function as claimed in the patent, or is that control properly attributed to the hardware maker, OS developer, or end-user?
- The case will also turn on a question of claim scope versus industry standard: Can the claim term "programmable address signal," which is disclosed in the patent as a specific address-loading mechanism, be construed broadly enough to cover the programming of mode-setting bits as implemented in the JEDEC LPDDR3 standard?
- Finally, a key evidentiary question for inducement will be intent: Does providing general hardware recommendations in a support article demonstrate the specific intent required to encourage infringement of the patented method, especially when the functionality is a standard feature of the recommended hardware?