Ocean Semiconductor LLC v. NVIDIA Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Ocean Semiconductor LLC (Delaware)
  • Defendant: NVIDIA Corporation (Delaware)
  • Plaintiff’s Counsel: Reichman Jorgensen Lehman & Feldberg LLP
• Case Identification: 6:22-cv-00200, W.D. Tex., 06/02/2022
• Venue Allegations: Plaintiff alleges venue is proper because NVIDIA is subject to personal jurisdiction in the district, maintains a "regular and established place of business" in Austin, Texas, and a substantial part of the events giving rise to the claim occurred in the district, including product announcements and the employment of design engineers.
• Core Dispute: Plaintiff alleges that Defendant’s graphics processing units (GPUs) and the methods for making them infringe three patents related to semiconductor fabrication, specifically concerning the formation of uniform silicide layers and strained silicon transistors.
• Technical Context: The patents address fundamental techniques for improving transistor performance and reliability in advanced integrated circuits, a critical factor in the competitive market for high-performance computing and graphics processors.
• Key Procedural History: The filing is a First Amended Complaint. The complaint alleges that NVIDIA was put on actual notice of the asserted patents and its alleged infringement upon service of the original complaint, forming the basis for the willfulness allegations.

Case Timeline

Date	Event
2003-07-07	Priority Date for U.S. Patent Nos. 7,005,376 and 7,307,322
2006-02-28	U.S. Patent No. 7,005,376 Issues
2006-07-31	Priority Date for U.S. Patent No. 7,629,211
2007-12-11	U.S. Patent No. 7,307,322 Issues
2009-12-08	U.S. Patent No. 7,629,211 Issues
2016-05-06	NVIDIA announces and demonstrates GeForce GTX 1080 in Austin, TX
2022-06-02	Plaintiff files First Amended Complaint for Patent Infringement

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,005,376 - "Ultra-Uniform Silicides in Integrated Circuit Technology," issued Feb. 28, 2006

The Invention Explained

• Problem Addressed: As transistors shrink, the electrical resistance between the metal contacts and the underlying silicon components (the source/drain junctions and the gate) increases, which can negatively impact the performance of the integrated circuit (’376 Patent, col. 2:21-28). Conventional methods of forming a conductive transition layer, known as a silicide, had not solved this problem of high resistance (’376 Patent, col. 2:42-51).
• The Patented Solution: The patent proposes a method for creating an "ultra-uniform" nickel silicide layer that is extremely thin and robust, which lowers electrical resistance and improves performance (’376 Patent, Abstract; col. 5:40-42). The solution runs counter to the "conventional wisdom" of the time by teaching that a very thin silicide layer, formed using a very low power and slow deposition process, provides superior results (’376 Patent, col. 5:16-38). The method involves a sequence of steps including forming the transistor gate and junctions, then forming the specific ultra-uniform silicide, and finally depositing dielectric layers and contacts (see ’376 Patent, Fig. 9).
• Technical Importance: The invention provides a specific manufacturing process to address the critical challenge of contact resistance, a fundamental bottleneck in scaling semiconductor devices to smaller nodes.

Key Claims at a Glance

• The complaint asserts independent claim 1 and dependent claims 4 and 6 (Compl. ¶32).
• Independent Claim 1 is a method claim with the following essential elements:
  • providing a semiconductor substrate;
  • forming a gate dielectric on the semiconductor substrate;
  • forming a gate over the gate dielectric;
  • forming source/drain junctions in the semiconductor substrate;
  • forming ultra-uniform silicides on the source/drain junctions;
  • depositing a dielectric layer above the semiconductor substrate; and
  • forming contacts in the dielectric layer to the ultra-uniform silicides.
• The complaint reserves the right to assert additional claims (Compl. ¶33).

U.S. Patent No. 7,307,322 - "Ultra-Uniform Silicide System in Integrated Circuit Technology," issued Dec. 11, 2007

The Invention Explained

• Problem Addressed: This patent, a divisional of the ’376 patent, addresses the same technical problem of high electrical resistance at the metal-silicon interface in modern transistors (’322 Patent, col. 2:30-36).
• The Patented Solution: Rather than claiming the method of making the device, the ’322 patent claims the resulting physical structure of the integrated circuit itself (’322 Patent, Abstract). The invention is an integrated circuit that includes "ultra-uniform silicides" on the source/drain junctions and gate, which are covered by a dielectric layer and connected by contacts, as depicted in the patent’s figures (see ’322 Patent, Fig. 8). The core inventive concept remains the specific nature of this ultra-uniform silicide layer (’322 Patent, col. 5:26-31).
• Technical Importance: This patent protects the final semiconductor product that embodies the structural benefits of the ultra-uniform silicide, complementing the method claims of its parent patent.

Key Claims at a Glance

• The complaint asserts independent claim 1 and dependent claims 2 and 4 (Compl. ¶52).
• Independent Claim 1 is an apparatus claim reciting an integrated circuit with the following essential components:
  • a semiconductor substrate having source/drain junctions;
  • a gate dielectric on the semiconductor substrate;
  • a gate over the gate dielectric;
  • ultra-uniform silicides on the source/drain junctions;
  • a dielectric layer above the semiconductor substrate; and
  • contacts in the dielectric layer to the ultra-uniform silicides.
• The complaint reserves the right to assert additional claims (Compl. ¶53).

U.S. Patent No. 7,629,211 - "Field Effect Transistor and Method of Forming a Field Effect Transistor," issued Dec. 8, 2009

• Technology Synopsis: This patent addresses the problem of reduced charge mobility in transistors by creating mechanical strain in the transistor’s channel region. It discloses a method of forming a "strain-creating element" in a cavity adjacent to the transistor’s gate electrode. The key aspect is that the chemical composition of this element has a concentration gradient, which is intended to prevent the undesirable relaxation of the strain and thereby maintain the performance boost (’211 Patent, Abstract; col. 4:30-40).
• Asserted Claims: Independent claim 1 and dependent claim 5 (Compl. ¶72).
• Accused Features: The complaint alleges that the process used to manufacture the Accused Products, particularly the formation of field effect transistors, meets the limitations of the ’211 patent claims (Compl. ¶75). This includes forming a cavity and then forming a strain-creating element with specific properties related to its chemical composition and concentration ratios (Compl. ¶75).

III. The Accused Instrumentality

Product Identification

The complaint names a wide range of NVIDIA semiconductor products, including but not limited to the GEFORCE RTX 20 SERIES, GEFORCE GTX 16 SERIES, TITAN, and QUADRO models (Compl. ¶9). The allegations group these under the umbrella of products incorporating "NVIDIA's Turing architecture" and/or products manufactured using "TSMC's 12nm FinFET manufacturing process" (Compl. ¶4, ¶9).

Functionality and Market Context

The accused products are high-performance GPUs used in consumer electronics, computers, automotive systems, and other industries (Compl. ¶7). The infringement allegations do not focus on the end-user functionality of the GPUs, but rather on the fundamental structure and manufacturing processes of the transistors within the chips themselves. The complaint alleges that these GPUs are designed by NVIDIA and manufactured on its behalf by foundry partners such as Taiwan Semiconductor Manufacturing Company Ltd. ("TSMC") (Compl. ¶8, ¶9).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

'376 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
A method of forming an integrated circuit comprising: providing a semiconductor substrate;	The manufacture of the Accused Products involves a process wherein a semiconductor substrate is provided.	¶35	col. 6:51-54
forming a gate dielectric on the semiconductor substrate;	A gate dielectric is formed on the semiconductor substrate.	¶35	col. 6:54-55
forming a gate over the gate dielectric;	A gate is formed over the gate dielectric.	¶35	col. 6:55-57
forming source/drain junctions in the semiconductor substrate;	Source/drain junctions are formed in the semiconductor substrate.	¶35	col. 6:6-11
forming ultra-uniform silicides on the source/drain junctions;	Ultra-uniform silicides are formed on the source/drain junctions.	¶35	col. 6:31-37
depositing a dielectric layer above the semiconductor substrate;	A dielectric layer is deposited above the semiconductor substrate.	¶35	col. 5:43-47
forming contacts in the dielectric layer to the ultra-uniform silicides.	Contacts are formed in the dielectric layer to the ultra-uniform silicides.	¶35	col. 5:47-48

Identified Points of Contention

• Factual Question: The central dispute will likely concern the limitation "forming ultra-uniform silicides." The complaint alleges this step occurs but provides no specific evidence (e.g., from microscopy or materials analysis) that the silicides in NVIDIA's products meet the patent's specific quantitative definition of "ultra-uniform," which is described as having "no variations in thickness greater than about 3% of the overall thickness" ('376 Patent, col. 5:18-20). The case may turn on whether discovery shows NVIDIA's manufacturing process results in this structure.
• Scope Question: A key legal question will be how broadly the term "ultra-uniform silicides" is construed. The patent links the term to specific formation conditions (e.g., low power deposition) and a very thin final layer (’376 Patent, col. 5:21-38). The infringement analysis will depend on whether the term is limited to silicides created under these specific conditions or can read on any silicide layer that is merely smooth or thin.

'322 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
An integrated circuit comprising: a semiconductor substrate having source/drain junctions;	The Accused Products include an integrated circuit comprising a semiconductor substrate having source/drain junctions.	¶55	col. 6:40-45
a gate dielectric on the semiconductor substrate;	The Accused Products include a gate dielectric on the semiconductor substrate.	¶55	col. 6:54-55
a gate over the gate dielectric;	The Accused Products include a gate over the gate dielectric.	¶55	col. 6:55-57
ultra-uniform silicides on the source/drain junctions;	The Accused Products include ultra-uniform silicides on the source/drain junctions.	¶55	col. 7:1-4
a dielectric layer above the semiconductor substrate; and	The Accused Products further include a dielectric layer above the semiconductor substrate.	¶55	col. 7:43-47
contacts in the dielectric layer to the ultra-uniform silicides.	The Accused Products have contacts in the dielectric layer to the ultra-uniform silicides.	¶55	col. 7:47-48

Identified Points of Contention

• Technical Question: As with the ’376 patent, the infringement analysis for this apparatus claim hinges on whether the final accused GPU chips contain "ultra-uniform silicides." The question for the court will be whether the physical structure of the NVIDIA chips, as manufactured, satisfies this limitation.
• Scope Question: The analysis will be sensitive to the same claim construction issues described for the ’376 patent, as the term "ultra-uniform silicides" is central to both patents.

V. Key Claim Terms for Construction

• The Term: "ultra-uniform silicides" (appears in ’376 patent, claim 1; ’322 patent, claim 1)
• Context and Importance: This term is the primary point of novelty asserted by the plaintiff for the '376 and '322 patents. The outcome of the infringement analysis for these two patents is almost entirely dependent on the construction of this term. Practitioners may focus on this term because the patent specification appears to give it a specific, quantitative meaning that may be difficult for the plaintiff to prove is met by the accused products.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party arguing for a broader scope may point to the general problem statement in the patent, which focuses on solving high resistance, and argue that "ultra-uniform" is a qualitative term of degree, meant to distinguish from rougher prior art silicides (’376 Patent, col. 2:42-45).
  • Evidence for a Narrower Interpretation: A party arguing for a narrower scope will heavily rely on the specification's explicit definition: "By definition, an ultra-uniform silicide means a layer of silicide where there are no variations in thickness greater than about 3% of the overall thickness" (’376 Patent, col. 5:18-20). This party would also point to the disclosure linking the formation of such silicides to very specific process parameters, such as a deposition power "below 500 watts" and a thickness of "not more than 50 Å" (’376 Patent, col. 5:25-38), arguing these limitations are integral to the term's meaning.

VI. Other Allegations

• Indirect Infringement: The complaint alleges NVIDIA induces infringement by its foundry partners (e.g., TSMC) and customers. It claims NVIDIA induces foundries by providing the designs and ordering the manufacture of the accused chips (Compl. ¶45, ¶65, ¶85). It alleges inducement of customers and end-users by providing marketing materials, technical specifications, and development tools that instruct on the use of the infringing products (Compl. ¶39, ¶59, ¶79).
• Willful Infringement: The complaint alleges willful infringement based on NVIDIA having actual knowledge of the patents and its infringement from "at least as of the date of service of the original Complaint" (Compl. ¶48, ¶68, ¶88). This is a post-suit willfulness allegation.

VII. Analyst’s Conclusion: Key Questions for the Case

This case appears to center on highly technical questions of semiconductor manufacturing and claim interpretation. The key questions for the court will likely be:

1. A core issue will be one of definitional scope and proof: Will the term "ultra-uniform silicides" be construed narrowly to require the specific "3% thickness variation" defined in the specification? If so, a key evidentiary question will be whether the plaintiff can demonstrate through technical analysis that the accused NVIDIA products, manufactured on an industrial scale, actually meet this precise structural requirement.
2. A second central question will be one of technological mapping: For the '211 patent, does the accused FinFET manufacturing process, a three-dimensional transistor architecture, create a "strain-creating element" that infringes claims written for what appears to be a planar transistor technology? This will require a detailed comparison of how strain is engineered in the patented method versus the accused process.
3. A third question involves divided infringement and inducement: Given that NVIDIA designs the chips but third-party foundries like TSMC manufacture them, the court will need to analyze the specific facts supporting inducement. A key issue will be whether NVIDIA's actions, such as providing design files and placing manufacturing orders, constitute the requisite specific intent to encourage another's infringement of the asserted method and apparatus claims.