DCT

6:22-cv-00200

Ocean Semiconductor LLC v. NVIDIA Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00200, W.D. Tex., 07/28/2022
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because NVIDIA maintains a regular and established place of business in Austin, employs engineers in the district, and has conducted product launches there. Venue is alleged to be proper for TSMC North America based on its permanent office in Austin, and for TSMC Ltd. as a foreign entity subject to suit in any U.S. judicial district.
  • Core Dispute: Plaintiff alleges that Defendant NVIDIA’s graphics processing units (GPUs) and related products, manufactured by Defendant TSMC, infringe three U.S. patents related to semiconductor fabrication methods and the resulting integrated circuit structures.
  • Technical Context: The patents relate to advanced semiconductor manufacturing techniques, including methods for reducing electrical resistance by forming highly uniform "silicide" layers and for improving transistor performance by creating mechanical strain in the silicon lattice.
  • Key Procedural History: This action was initiated via a Second Amended Complaint. The complaint alleges that Defendants had actual notice of the asserted patents and their infringement at least as of the date of service of the original complaint, forming the basis for allegations of willful infringement.

Case Timeline

Date Event
2003-07-07 Priority Date for ’376 and ’322 Patents
2006-02-28 Issue Date for U.S. Patent No. 7,005,376
2006-07-31 Priority Date for ’211 Patent
2007-12-11 Issue Date for U.S. Patent No. 7,307,322
2009-12-08 Issue Date for U.S. Patent No. 7,629,211
2016-05-06 NVIDIA product announcement in Austin, TX (GeForce GTX 1080)
2022-07-28 Second Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,005,376 - "Ultra-Uniform Silicides in Integrated Circuit Technology"

The Invention Explained

  • Problem Addressed: As transistors shrink, the electrical resistance between the metal contacts and the silicon substrate or polysilicon gate increases, which degrades the performance of the integrated circuit (’376 Patent, col. 2:20-30). Conventional methods for creating a conductive transition layer, known as a "silicide," were not solving the problem of high resistance between the metal contacts and the silicide itself (’376 Patent, col. 2:48-50).
  • The Patented Solution: The patent discloses a method of forming an "ultra-uniform" silicide layer, specifically a nickel silicide, to create a more robust and lower-resistance connection. The method involves a very low power (below 500 watts) and extra slow (below 7.0 Å/second) vapor deposition process to create an "ultra-thin" nickel layer (not more than 50 Å thick) that is then converted to silicide (’376 Patent, col. 5:25-45). This process results in a silicide layer with thickness variations of no more than about 3% (’376 Patent, col. 5:20-25).
  • Technical Importance: This method provided a potential solution for overcoming a key physical barrier—contact resistance—in the ongoing miniaturization and performance scaling of semiconductor devices. (Compl. ¶28).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 7, and dependent claims 4 and 6. (Compl. ¶41, ¶43).
  • Independent Claim 1 recites a method of forming an integrated circuit with the following essential elements:
    • providing a semiconductor substrate;
    • forming a gate dielectric on the semiconductor substrate;
    • forming a gate over the gate dielectric;
    • forming source/drain junctions in the semiconductor substrate;
    • forming ultra-uniform silicides on the source/drain junctions;
    • depositing a dielectric layer above the semiconductor substrate; and
    • forming contacts in the dielectric layer to the ultra-uniform silicides.

U.S. Patent No. 7,307,322 - "Ultra-Uniform Silicide System in Integrated Circuit Technology"

The Invention Explained

  • Problem Addressed: The ’322 Patent, a divisional of the ’376 Patent, addresses the same problem of high electrical resistance in miniaturized transistors that negatively impacts performance. (’322 Patent, col. 2:31-36, 54-58).
  • The Patented Solution: Instead of claiming the method, this patent claims the resulting physical structure of an integrated circuit. The invention is an integrated circuit that incorporates the "ultra-uniform" silicide layer between the source/drain junctions and the metal contacts. The specification defines this silicide layer as having no thickness variations greater than 3% of the overall thickness (’322 Patent, Abstract; col. 5:31-35).
  • Technical Importance: The patent claims a specific, tangible transistor architecture that embodies the solution of reduced contact resistance, providing a structural benchmark for high-performance semiconductor devices. (Compl. ¶32).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 5, and dependent claims 2 and 4. (Compl. ¶62, ¶64).
  • Independent Claim 1 recites an integrated circuit with the following essential elements:
    • a semiconductor substrate having source/drain junctions;
    • a gate dielectric on the semiconductor substrate;
    • a gate over the gate dielectric;
    • ultra-uniform silicides on the source/drain junctions;
    • a dielectric layer above the semiconductor substrate; and
    • contacts in the dielectric layer to the ultra-uniform silicides.

U.S. Patent No. 7,629,211 - "Field Effect Transistor and Method of Forming a Field Effect Transistor"

  • Technology Synopsis: The patent describes a method to improve transistor performance by increasing the mobility of charge carriers in the transistor's channel. This is achieved by forming a "strain-creating element" (e.g., silicon-germanium) in a cavity adjacent to the gate electrode. The key innovation is forming this element with a graded chemical composition, where the concentration of the strain-inducing element (e.g., germanium) increases with distance from the substrate, which is intended to reduce crystal defects and prevent strain relaxation. (’211 Patent, col. 4:32-43, Abstract; Compl. ¶36).
  • Asserted Claims: Independent claim 1 and dependent claim 5. (Compl. ¶83, ¶85).
  • Accused Features: The complaint alleges that the process used to manufacture the accused GPUs includes forming transistors with strain-creating elements that have the claimed graded concentration profile. (Compl. ¶86).

III. The Accused Instrumentality

Product Identification

The accused products are NVIDIA semiconductor products, including but not limited to, the GEFORCE RTX 20 SERIES, GEFORCE GTX 16 SERIES, TITAN, and QUADRO model GPUs (Compl. ¶14). The complaint specifically identifies products incorporating NVIDIA’s "Turing architecture" and manufactured using TSMC’s 12nm FinFET process (Compl. ¶14). The claim charts attached as exhibits focus on the NVIDIA GeForce RTX 2070 Super (TU104 GPU) as an exemplary product (Compl. ¶¶45, 66, 87).

Functionality and Market Context

The accused products are high-performance GPUs designed and sold by NVIDIA and fabricated by its foundry partner, TSMC (Compl. ¶13). The complaint alleges that these integrated circuits are manufactured using processes and contain structures, such as ultra-uniform silicides and graded strain-creating elements, that are central to their performance and infringe the patents-in-suit (Compl. ¶¶44, 65, 86). The complaint positions these products as serving major markets including high-performance computing, automotive electronics, and the Internet of Things (IoT) (Compl. ¶8, ¶12). A TEM image in the complaint shows the silicon substrate from which fins are formed in the accused products (Compl. Ex. 4, p. 78).

IV. Analysis of Infringement Allegations

’376 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method of forming an integrated circuit comprising: providing a semiconductor substrate; The manufacture of the Accused Products involves providing a semiconductor substrate, such as silicon, from which fins are formed. ¶44; Ex. 4, p. 78 col. 3:51-54
forming a gate dielectric on the semiconductor substrate; A gate dielectric, including an oxide interfacial layer and a high-k dielectric like hafnium oxide, is formed on the substrate over the fin. ¶44; Ex. 4, p. 79 col. 3:55-59
forming a gate over the gate dielectric; A metal gate is formed over the gate dielectric and the fin. ¶44; Ex. 4, p. 80 col. 3:59-61
forming source/drain junctions in the semiconductor substrate; Source and drain junctions are formed in the upper portions of the fin on opposite sides of the gate. ¶44; Ex. 4, p. 81 col. 4:1-11
forming ultra-uniform silicides on the source/drain junctions, An ultra-uniform silicide layer, defined as having no thickness variations greater than about 3% of the overall thickness, is formed on the junctions. ¶44; Ex. 4, p. 82 col. 5:20-25
depositing a dielectric layer above the semiconductor substrate; and A dielectric layer is deposited at the contact level above the substrate. ¶44; Ex. 4, p. 82 col. 5:46-52
forming contacts in the dielectric layer to the ultra-uniform silicides. Contacts are formed in the dielectric layer to connect to the ultra-uniform silicides. ¶44; Ex. 4, p. 83 col. 6:1-5

Identified Points of Contention

  • Scope Questions: A central question will be whether the manufacturing process used by TSMC meets the specific deposition parameters for forming "ultra-uniform silicides" as described in the ’376 Patent specification (e.g., low power, slow rate, specific thickness) or if producing a resulting structure with the defined uniformity is sufficient for infringement of the method claim.
  • Technical Questions: What evidence does the complaint provide that TSMC's proprietary 12nm FinFET manufacturing process uses the specific low-power, slow-rate deposition steps required by the patent's detailed description to form the claimed silicide? The complaint’s evidence focuses on the resulting structure rather than the specific process steps.

’322 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
An integrated circuit comprising: a semiconductor substrate having source/drain junctions; The Accused Products contain a silicon semiconductor substrate with source and drain junctions formed in the upper portions of a fin. ¶65; Ex. 5, p. 88 col. 6:47-48
a gate dielectric on the semiconductor substrate; The Accused Products contain a gate dielectric with an oxide interfacial layer and a high-k dielectric over the fin. ¶65; Ex. 5, p. 89 col. 6:48-49
a gate over the gate dielectric; The Accused Products contain a replacement metal gate formed over the gate dielectric and fin. ¶65; Ex. 5, p. 90 col. 6:49-50
ultra-uniform silicides on the source/drain junctions; The Accused Products contain a layer of silicide on the source/drain junctions with thickness variations not greater than 3% of the overall thickness. ¶65; Ex. 5, p. 91 col. 5:31-35
a dielectric layer above the semiconductor substrate; and The Accused Products contain a dielectric layer at the contact level above the substrate. ¶65; Ex. 5, p. 92 col. 6:51-52
contacts in the dielectric layer to the ultra-uniform silicides. The Accused Products contain contacts formed in the dielectric layer that connect to the ultra-uniform silicides. ¶65; Ex. 5, p. 93 col. 6:52-54

Identified Points of Contention

  • Scope Questions: Does the term "ultra-uniform," which the patent defines as having "no variations in thickness greater than 3% of the overall thickness," read on the physical silicide layers present in the accused GPUs? The complaint presents a TEM image showing the alleged ultra-uniform silicide layer (Compl. Ex. 5, p. 91).
  • Technical Questions: What is the measurement methodology for determining the thickness variation of the silicide layer in the accused products, and will it be sufficient to prove that any variations are less than the claimed 3% threshold?

V. Key Claim Terms for Construction

The Term: "ultra-uniform silicides"

  • Context and Importance: This term is the central limitation in the independent claims of both the ’376 and ’322 patents. The definition of this term will be critical to the infringement analysis for both the asserted method and structure claims. Practitioners may focus on this term because the specification provides an explicit, quantitative definition.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent's "Disclosure of the Invention" section states the method "significantly increases robustness and lowers the electrical resistance," which could support an argument that the term should be construed functionally to mean any silicide that achieves these results. (’376 Patent, col. 2:58-63).
    • Evidence for a Narrower Interpretation: The specification provides an explicit definition: "By definition, an ultra-uniform silicide means a layer of silicide where there are no variations in thickness greater than about 3% of the overall thickness." (’376 Patent, col. 5:20-25). This express definition is likely to be a controlling piece of intrinsic evidence.

The Term: "forming ultra-uniform silicides"

  • Context and Importance: This is the key process step in claim 1 of the ’376 Patent. The construction of this term will determine whether infringement requires practicing the specific deposition technique disclosed in the patent or merely achieving the resulting structure.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party could argue the claim language itself does not recite specific process parameters (e.g., power levels, deposition rates), and therefore any method that results in a silicide meeting the "ultra-uniform" definition infringes.
    • Evidence for a Narrower Interpretation: The specification describes a single, highly specific embodiment for achieving the invention: "by depositing the nickel... by a very low power vapor deposition process, where the very low power means a power level below 500 watts... an extra slow rate of metal deposition... below 7.0 Å per second... to an ultra-thin thickness of not more than 50 Å." (’376 Patent, col. 5:25-45). A party may argue that these details limit the scope of the method step under claim construction principles.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges inducement against both NVIDIA and TSMC. The allegations are based on Defendants actively encouraging suppliers, manufacturers, and customers to make, use, sell, and import the infringing products through marketing materials, technical specifications, data sheets, user manuals, and developer support forums. (Compl. ¶¶47-49, 68-70, 89-91).
  • Willful Infringement: The complaint alleges willful infringement against Defendants based on knowledge of the patents and the alleged infringement occurring at least as of the date of service of the original complaint. (Compl. ¶¶58, 79, 100).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of definitional scope and proof: Can the term "ultra-uniform silicide" be proven to read on the accused products? This will require resolving whether the patent's explicit quantitative definition—"no variations in thickness greater than about 3% of the overall thickness"—is the controlling construction, and whether Plaintiff's technical evidence can meet that high standard.
  • A key legal question for the ’376 method patent will be one of process versus product: Does infringement of the "forming" step require practicing the specific low-power, slow-rate deposition process detailed in the specification, or is it sufficient to show that the accused manufacturing method simply produces a silicide layer that meets the structural definition of "ultra-uniform"?
  • A central evidentiary question for the ’211 patent will be one of demonstrating the gradient: Can Plaintiff prove, through analysis of the accused devices, that the strain-creating elements contain a graded concentration of materials that "increases in a vertical direction with increasing distance from a bottom surface," as claimed? The complaint provides a graph purporting to show this relationship, which will likely be a focal point of expert discovery. (Compl. Ex. 6, p. 104).