DCT

6:22-cv-00385

Acqis LLC v. Microsoft Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00385, W.D. Tex., 04/14/2022
  • Venue Allegations: Plaintiff alleges venue is proper in the Western District of Texas because Microsoft maintains regular and established places of business in the district, employs numerous personnel, and commits acts of patent infringement by making, using, and selling the accused products within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s computer products, including its Surface line and Xbox consoles, infringe five patents related to the use of low-voltage differential signaling (LVDS) for high-speed serial data transfer in computer bus technologies like PCI Express (PCIe) and USB 3.x.
  • Technical Context: The dispute centers on high-speed data interconnects, such as PCIe and USB, which are fundamental technologies for connecting core components like CPUs, memory, and peripherals in modern computers, with significant market implications for performance and power efficiency.
  • Key Procedural History: The complaint alleges that Plaintiff provided Microsoft with actual notice of the asserted patents and accused product lines via a letter received on May 18, 2018. It also notes that the asserted patents have been licensed to other major technology companies and have survived multiple challenges before the Patent Trial and Appeal Board (PTAB), where petitions for inter partes review were denied institution.

Case Timeline

Date Event
1999-05-14 Earliest Priority Date for all five Patents-in-Suit
2003-11-04 Issue Date of U.S. Patent No. 6,643,777 (reissued as '654 and '140)
2013-12-17 U.S. Patent No. RE44,654 Issued
2014-09-16 U.S. Patent No. RE45,140 Issued
2015-03-10 U.S. Patent No. 8,977,797 Issued
2016-12-27 U.S. Patent No. 9,529,768 Issued
2017-07-11 U.S. Patent No. 9,703,750 Issued
2018-05-18 Plaintiff alleges Microsoft received actual notice of infringement
2022-04-14 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,529,768 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

Issued December 27, 2016 (Compl. ¶13).

The Invention Explained

  • Problem Addressed: The patent family’s background describes the limitations of prior art computer interfaces, such as those connecting notebook computers to docking stations using the Peripheral Component Interconnect (PCI) bus protocol. These parallel interfaces required a large number of conductive lines and connector pins, making them bulky, costly, and not "cable friendly" for flexible connections ('797 Patent, col. 3:12-41).
  • The Patented Solution: The invention proposes replacing the parallel PCI bus interface with a high-speed, serial, low-voltage differential signal (LVDS) channel (’797 Patent, col. 5:50-55). This is achieved by encoding parallel PCI bus signals (including address, data, and control signals) into serial bitstreams for transmission over the LVDS channel and decoding them at the receiving end (’797 Patent, col. 5:35-41). This architecture, depicted in embodiments like the Host Interface Controller and Peripheral Interface Controller of Figure 9, reduces pin count and enables more efficient, cabled high-speed communication between computer subsystems (’797 Patent, Fig. 9).
  • Technical Importance: This approach enabled the development of faster, more power-efficient, and physically smaller high-speed interconnects compared to the parallel bus interfaces they were designed to replace (Compl. ¶¶2, 20).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶56).
  • Essential elements of Claim 1:
    • A computer comprising an integrated central processing unit, interface controller, and Phase-Locked Loop (PLL) clock circuitry in a single chip.
    • A first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller.
    • The LVDS channel conveys address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form.
    • The LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair for the opposite direction.
    • The PLL clock circuitry generates different clock frequencies used to convey the PCI bus transactions through the LVDS channel.
  • The complaint reserves the right to assert additional claims (Compl. ¶56).

U.S. Patent No. 9,703,750 - "Computer System Including CPU or Peripheral Bridge Directly Connected to a Low Voltage Differential Signal Channel that Communicates Serial Bits of a Peripheral Component Interconnect Bus Transaction in Opposite Directions"

Issued July 11, 2017 (Compl. ¶14).

The Invention Explained

  • Problem Addressed: Similar to the ’768 Patent, this patent addresses the physical and electrical limitations of wide, parallel bus interfaces like PCI, which were cumbersome and inefficient for connecting computer components ('797 Patent, col. 3:12-41).
  • The Patented Solution: The patent describes a computer system architecture where an integrated CPU and interface controller are directly coupled to system memory and also directly connected to a high-speed serial LVDS channel. This channel is structured with opposing unidirectional signal pairs to handle bidirectional communication, transmitting not only address and data bits but also byte enable information from a PCI bus transaction (’797 Patent, col. 5:35-41, col. 19:43-48). This integration simplifies the system architecture while improving data throughput.
  • Technical Importance: This technology relates to the integration of high-speed serial links directly into the core processor and memory controller complex, a foundational step in modern System-on-a-Chip (SoC) design that improves performance and reduces physical footprint (Compl. ¶¶2, 20).

Key Claims at a Glance

  • The complaint asserts at least independent claim 1 (Compl. ¶85).
  • Essential elements of Claim 1:
    • A computer system with an integrated central processing unit and interface controller in a single chip.
    • A system memory directly coupled to the integrated CPU and interface controller.
    • A first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller.
    • The LVDS channel conveys address bits, data bits, and byte enable information of a PCI bus transaction in a serial bit stream.
    • The LVDS channel comprises a first unidirectional, differential signal pair for one direction and a second unidirectional, differential signal pair for the opposite direction.
  • The complaint reserves the right to assert additional claims (Compl. ¶85).

U.S. Patent No. 8,977,797 - "Method of Improving Peripheral Component Interface Communications Utilizing a Low Voltage Differential Signal Channel"

Issued March 10, 2015 (Compl. ¶15).

  • Technology Synopsis: This patent claims methods for improving data throughput in PCI communications by utilizing an LVDS channel with bidirectional serial paths. The claimed method involves conveying encoded address and data bits from a PCI bus transaction over these serial channels and increasing data throughput by providing each channel with multiple pairs of differential signal lines ('797 Patent, col. 38:55-66).
  • Asserted Claims: At least independent claim 14 is asserted (Compl. ¶110).
  • Accused Features: The complaint alleges that Microsoft's manufacturing and testing of products like the Surface Pro 6 infringes this method. The accused acts include connecting an LVDS channel (the PCIe 3.0 interface) directly to the CPU, using multiple pairs of differential signal lines (multiple PCIe lanes) to increase data throughput, and conveying encoded PCI bus transaction data serially between the CPU and the NVMe SSD (Compl. ¶¶115, 120-121).

U.S. Patent No. RE44,654 - "Data Security Method and Device for Computer Modules"

Issued December 17, 2013 (Compl. ¶16).

  • Technology Synopsis: This patent claims a method for increasing a computer's external data communication speed. The method involves providing a computer with an integrated CPU and graphics controller connected to a first LVDS channel for internal communications. A connector is also provided to couple a second LVDS channel to an external console, with this second channel comprising bidirectional serial channels that enable Universal Serial Bus (USB) protocol data to be conveyed ('654 Patent, col. 2:58-67, col. 3:1-6).
  • Asserted Claims: At least independent claim 20 is asserted (Compl. ¶136).
  • Accused Features: The complaint accuses the manufacturing of products like the Surface Pro 6, which allegedly practice the claimed method by providing an integrated CPU/graphics controller (Intel Core i5-8250U), connecting a first LVDS channel (PCIe) to it, and providing a second LVDS channel via a connector (the USB 3.0 port) to convey USB protocol data to external devices (Compl. ¶¶140-141, 145-146, 150).

U.S. Patent No. RE45,140 - "Data Security Method and Device for Computer Modules"

Issued September 16, 2014 (Compl. ¶17).

  • Technology Synopsis: This patent claims methods for improving computer performance by directly connecting multiple differential signal channels to a single-chip integrated CPU and graphics controller. The claimed method includes connecting a first LVDS channel for internal components, a separate differential signal channel to output video data, and a second LVDS channel coupled to a connector for external peripherals ('140 Patent, col. 2:58-67, col. 3:18-28).
  • Asserted Claims: At least independent claim 35 is asserted (Compl. ¶164).
  • Accused Features: The complaint alleges infringement by the manufacturing of products like the Surface Pro 6. The accused acts include obtaining an integrated CPU/graphics controller and connecting it directly to a first LVDS channel (the PCIe interface), a separate differential channel for video output (e.g., eDP/DisplayPort), and a second LVDS channel coupled to a connector for external peripherals (the USB 3.0 port) (Compl. ¶¶169-170, 174, 178-179).

III. The Accused Instrumentality

Product Identification

The complaint identifies Microsoft computer products and devices that include PCI Express (PCIe) and/or USB 3.x functionality. Specific product lines named include the Xbox game console and the Surface series (e.g., Surface Book, Surface Pro, Surface Laptop, Surface Studio, and Surface Hub) (Compl. ¶41). The infringement analysis uses the Microsoft Surface Pro 6 computer as a representative example (Compl. ¶57).

Functionality and Market Context

The complaint alleges the Surface Pro 6 utilizes an Intel Core i5-8250U processor, which integrates the CPU, interface controller, and PLL clock circuitry into a single chip (Compl. ¶60). This processor is alleged to support on-chip PCIe 3.0 and USB 3.0 functionality (Compl. ¶¶62, 147). The PCIe 3.0 interface is used to directly connect an NVMe solid-state drive (SSD) to the processor, allegedly forming a multi-lane LVDS channel that conveys serialized PCI bus transactions (Compl. ¶¶66-68). An illustrative diagram in the complaint shows the bi-directional lanes of a PCIe link between two devices (Compl. p. 22; Silicon Labs AN562). The device also includes a USB 3.0 port, which is alleged to constitute a second LVDS channel for connecting to external devices and conveying USB protocol data (Compl. ¶¶145-146, 148). Plaintiff alleges that Microsoft's "More Personal Computing" segment, which includes these products, generated approximately $54 billion in global revenue in fiscal year 2021 (Compl. ¶35).

IV. Analysis of Infringement Allegations

9,529,768 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a computer... The Microsoft Surface Pro 6 is a computer. ¶59 col. 35:20-22
comprising an integrated central processing unit, interface controller and Phase-Locked Loop (PLL) clock circuitry in a single chip... The Surface Pro 6 contains an Intel Core i5-8250U processor, which is alleged to integrate these three components into a single chip. ¶60 col. 36:50-55
a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller... The processor has an on-chip PCIe 3.0 interface that directly connects an NVMe SSD to the processor chip. This PCIe interface is alleged to be the claimed LVDS channel. ¶¶64, 66-67 col. 36:23-26
wherein the first LVDS channel conveys address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in a serial form... The PCIe interface transmits data, including address and data bits from Transaction Layer Packets (TLPs), in a serial format between the processor and the SSD. ¶¶67, 69 col. 36:35-41
wherein the first LVDS channel comprises a first unidirectional, differential signal pair... and a second unidirectional, differential signal pair... in a second, opposite direction... Each lane of the PCIe interface is alleged to contain a first unidirectional, differential signal pair (Tx) and a second unidirectional, differential signal pair (Rx) to convey data in opposite directions. An exemplary diagram shows these Tx and Rx pairs forming a PCIe lane (Compl. p. 22). ¶68 col. 36:30-35
wherein the PLL clock circuitry generates different clock frequencies, which are used to convey the PCI bus transactions through the LVDS channel. The PHY for the PCIe interface in the processor is alleged to include PLL clock circuitry that generates at least two different clock frequencies, such as a high-speed bitrate clock (e.g., 8 GT/s) and a lower-speed PIPE interface clock (e.g., 125/250 MHz), both of which are used in the process of conveying the transaction data. ¶70 col. 41:16-24

9,703,750 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A computer system... The Microsoft Surface Pro 6 is a computer system. ¶88 col. 35:20-22
comprising an integrated central processing unit and interface controller in a single chip... The Surface Pro 6 contains an Intel Core i5-8250U processor, which is alleged to be a single chip containing an integrated CPU and an interface controller (e.g., a PCIe controller within its "System Agent" section). ¶89 col. 36:50-55
a system memory directly coupled to the integrated central processing unit and interface controller... The Surface Pro 6 contains system memory (RAM) that is directly coupled to the processor, which contains a memory controller. A diagram shows the memory controller as part of the processor's "System Agent" (Compl. p. 35). ¶¶90, 96 col. 34:56-61
a first Low Voltage Differential Signal (LVDS) channel directly extending from the interface controller... The processor's on-chip PCIe 3.0 interface, which connects to the NVMe SSD, is alleged to be the claimed LVDS channel extending from the interface controller. ¶¶91, 93 col. 36:23-26
wherein the first LVDS channel conveys address bits, data bits, and byte enable information of a Peripheral Component Interconnect (PCI) bus transaction... The data transmitted over the serial PCIe interface is alleged to include address bits, data bits, and byte enable ("BE") information contained within Transaction Layer Packets (TLPs). ¶95 col. 19:43-48
wherein the first LVDS channel comprises a first unidirectional, differential signal pair... and a second unidirectional, differential signal pair... in a second, opposite direction. Each lane in the PCIe interface is alleged to contain a first unidirectional, differential signal pair for transmitting data and a second for receiving data, enabling communication in opposite directions. ¶94 col. 36:30-35

Identified Points of Contention

  • Scope Questions: A central issue may be whether the term "Low Voltage Differential Signal (LVDS) channel," as defined and used in the patents, can be construed to read on the standardized Physical Layer of an industry-standard PCI Express or USB 3.x interface. The defense may argue that PCIe and USB are distinct technologies developed in parallel to, not as implementations of, the patents' specific "XPBus" architecture.
  • Technical Questions: For the ’768 patent, a question is whether the accused processor's generation of both a high-speed bitrate clock and a lower-speed PIPE interface clock meets the limitation that "different clock frequencies... are used to convey the PCI bus transactions." The analysis may focus on whether both frequencies are truly used for "conveyance" over the channel, or if one is merely an internal interface clock for the controller logic.

V. Key Claim Terms for Construction

"Low Voltage Differential Signal (LVDS) channel"

  • Context and Importance: The definition of this term is fundamental to the dispute. Plaintiff's infringement theory equates the physical layers of industry standards PCIe and USB 3.x with the claimed "LVDS channel." The viability of this theory depends on whether the term is interpreted broadly as a generic descriptor for high-speed serial differential signaling, or narrowly as limited to the specific "XPBus" architecture disclosed in the patents.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification of the parent '797 patent explicitly states: "The term LVDS is herein used to generically refer to low voltage differential signals and is not intended to be limited to any particular type of LVDS technology" ('797 Patent, col. 4:3-6). This language may support an interpretation that covers any interface using the general principles of LVDS, including PCIe and USB.
    • Evidence for a Narrower Interpretation: The detailed description focuses almost exclusively on a specific proprietary interface termed the "XPBus," complete with its own Host and Peripheral Interface Controllers (HIC/PIC) and signaling protocols ('797 Patent, Fig. 9; Fig. 12-14). A party could argue that the claims, when read in light of the specification as a whole, are implicitly limited to this disclosed architecture and its functional equivalents, not broad industry standards.

"directly extending from the interface controller"

  • Context and Importance: This term relates to the physical and logical architecture of the connection within the single-chip processor. Practitioners may focus on this term because its construction will determine whether a logical connection between functional blocks within a complex System-on-a-Chip (SoC) satisfies the "directly extending" requirement, or if a more literal physical connection is needed.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Figures in the patent family, such as Figure 8B of the '797 patent, depict a "Single Chip Fully Integrated" module where the CPU, Graphics Controller, and Interface Controller are combined. In such a design, connections between functional blocks are inherently direct from a logical standpoint, which may support a broader reading.
    • Evidence for a Narrower Interpretation: The complaint's own supporting diagrams show the PCIe controller as a block within a larger "System Agent" section of the processor chip (Compl. p. 19). This could be used to argue that there is intervening logic between the core controller and the physical I/O pins, suggesting the channel does not "directly extend" from the controller itself in a strict physical sense.

VI. Other Allegations

Indirect Infringement

The complaint alleges induced infringement, asserting that Microsoft sells the accused products to third parties (e.g., retailers, end users) and provides instructions through user manuals and support websites on how to use the products in their normal, infringing manner (e.g., by powering on the device or using its USB ports) (Compl. ¶¶49, 76-77).

Willful Infringement

The willfulness allegations are predicated on alleged pre-suit knowledge. The complaint states that Microsoft received a notice letter on or around May 18, 2018, that identified all five patents-in-suit and the accused product lines. The complaint alleges that Microsoft's continued sales of these products after receiving notice constitutes deliberate and egregious conduct (Compl. ¶¶41, 43-44).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of technological scope: can the patents’ claims, which describe a bespoke LVDS-based bus interface termed "XPBus," be construed to cover the industry-standard PCI Express and USB 3.x physical layer implementations found in the accused products, or will these be successfully characterized as distinct, non-infringing technologies?
  • A critical legal question will be the construction of key terms, particularly "Low Voltage Differential Signal (LVDS) channel." The case may turn on whether this term is given a broad, generic meaning as suggested by the patent's own definitional statement, or a narrower meaning implicitly limited by the specific "XPBus" embodiments detailed in the specification.
  • Given the allegation that Microsoft had actual notice of the patents and accused product lines as of May 2018, a significant focus will likely be on willful infringement. The evidence surrounding Microsoft's response, or lack thereof, to the 2018 notice letter will be central to the potential for enhanced damages.