Mallard IP LLC v. BOXX Tech LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mallard IP LLC (Texas)
  • Defendant: Boxx Technologies LLC (Delaware)
  • Plaintiff’s Counsel: Kent & Risley LLC
• Case Identification: 6:22-cv-00433, W.D. Tex., 04/29/2022
• Venue Allegations: Plaintiff alleges venue is proper because Defendant has a regular and established place of business in the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s Apexx A3 workstation infringes a patent related to dynamically reconfigurable digital circuit blocks.
• Technical Context: The technology concerns a specific architecture for programmable circuits, intended to provide more cost-effective and flexible performance for microcontroller applications compared to traditional Field-Programmable Gate Arrays (FPGAs).
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,603,330 - "Configuring Digital Functions in a Digital Configurable Macro Architecture"

• Patent Identification: U.S. Patent No. 6,603,330, “Configuring Digital Functions in a Digital Configurable Macro Architecture,” issued August 5, 2003.

The Invention Explained

• Problem Addressed: The patent identifies a need for programmable digital circuits in cost-sensitive microcontroller applications. It notes that conventional Field-Programmable Gate Arrays (FPGAs) are often "highly inefficient with respect to chip area, increasing their cost" and that reprogramming their look-up tables is a "time consuming task." (’330 Patent, col. 1:46-53).
• The Patented Solution: The invention proposes a "programmable digital circuit block" that is not a generic, fully programmable device like an FPGA, but is instead designed to be configured to perform any one of a variety of predetermined digital functions (e.g., timers, counters, communication ports) (’330 Patent, col. 2:1-12). Configuration is achieved quickly by changing the contents of a small number of "configuration registers," allowing the block to be "dynamically configurable from one predetermined digital function to another... for real-time processing" (’330 Patent, col. 2:28-34; Fig. 1). The circuit components within the block are designed for reuse across these different functions to minimize the physical size and cost of the chip (’330 Patent, col. 2:5-8).
• Technical Importance: This architecture aimed to provide a flexible, dynamically reconfigurable, and cost-effective solution for control-oriented applications common in consumer electronics, automotive systems, and other embedded devices (’330 Patent, col. 1:21-30).

Key Claims at a Glance

• The complaint asserts independent claim 25 (’330 Patent, col. 10:55-68; Compl. ¶16).
• The essential elements of independent claim 25, a method claim, are:
  • loading a plurality of configuration data corresponding to one of a plurality of predetermined digital functions into a configuration register of a programmable digital circuit block;
  • configuring the programmable digital circuit block to perform that predetermined digital function based on the configuration data;
  • wherein the loading and configuring steps are dynamically performed; and
  • wherein the programmable digital circuit block includes a data register for storing data to facilitate performing the function.
• The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

• The complaint identifies "Defendant's Apexx A3" as an exemplary infringing product (Compl. ¶16).

Functionality and Market Context

• The complaint identifies the Apexx A3 by name but provides no specific allegations regarding its technical functionality, internal architecture, or the specific components accused of infringement (Compl. ¶16). Public information suggests the Apexx A3 is a high-performance computer workstation, a different product category from the low-cost microcontrollers that are the focus of the '330 patent’s background section. The complaint does not provide sufficient detail for analysis of the accused product's relevant technical features.

IV. Analysis of Infringement Allegations

The complaint alleges infringement based on a preliminary claim chart (Exhibit B) that was incorporated by reference but not attached to the publicly filed complaint (Compl. ¶16). As such, an element-by-element analysis based on the plaintiff's specific theories is not possible from the provided documents. The infringement count asserts that Defendant has infringed at least claim 25 of the ’330 patent "either literally or under the doctrine of equivalents" (Compl. ¶16).

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Scope Questions: A primary question may be whether a component within a high-performance workstation like the Apexx A3 constitutes a "programmable digital circuit block" as contemplated by the patent. The patent's specification consistently frames the invention in the context of cost-sensitive "microcontroller or controller designs" (’330 Patent, col. 2:61-62). The defense may argue that the architecture of a modern, complex CPU or system-on-a-chip (SoC) in a workstation is technically distinct from the specific, reusable, and minimalist block described in the patent.
  • Technical Questions: The complaint does not identify which specific hardware in the Apexx A3 is the accused "programmable digital circuit block," what constitutes the "plurality of predetermined digital functions," or how those functions are "dynamically performed" in a manner consistent with the patent's emphasis on real-time reconfiguration. The plaintiff would need to provide evidence demonstrating that a component in the accused product performs the specific steps of the method claim, including dynamic loading of configuration data to switch between discrete, predetermined hardware functions.

V. Key Claim Terms for Construction

• The Term: predetermined digital functions

• Context and Importance: This term is central to the patent's asserted novelty over general-purpose FPGAs. The scope of infringement will depend on whether this term is limited to the class of functions described in the patent or can encompass a wider range of functionalities found in modern processors.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue that the term is not limited by the examples in the specification and covers any digital function that was designed into the hardware at the time of manufacture, as opposed to being defined later by a user.
  • Evidence for a Narrower Interpretation: The specification provides an explicit list of exemplary functions, including "a timer, a counter, a pulse width modulator (PWM), a cyclic redundancy generator/checker (CRC), a pseudo random sequence generator (PRS), a dead zone delay, a UART transmitter, a UART receiver, a SPI Master, and a SPI Slave" (’330 Patent, col. 8:42-47). A party could argue the term should be construed as being limited to this class of lower-level, embedded-system-type functions.

• The Term: dynamically performed

• Context and Importance: This term relates to the speed and manner of reconfiguring the circuit block. Its construction will determine how immediate and frequent the reconfiguration must be to meet the claim limitation, a key feature distinguished from the "time consuming task" of reprogramming FPGAs (’330 Patent, col. 1:52-53).

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party could argue this simply means the configuration can be changed at any time after the device is powered on, without requiring a full system reset.
  • Evidence for a Narrower Interpretation: The specification repeatedly links dynamic configuration to "real-time processing" and gives the example of reconfiguring a block "as a timer for a first length of time, re-configured as a counter for a second length of time" during operation (’330 Patent, col. 5:23-27). This may support a narrower construction requiring on-the-fly reconfiguration to perform different tasks within a single, continuous process.

VI. Other Allegations

• Indirect Infringement: The complaint does not allege facts to support, or include a count for, indirect infringement.
• Willful Infringement: The complaint does not include a specific count for willful infringement or allege facts supporting pre-suit knowledge by the Defendant. The prayer for relief includes a request for attorneys' fees pursuant to 35 U.S.C. § 285, which requires a finding that the case is "exceptional" (Compl., Prayer for Relief ¶D).

VII. Analyst’s Conclusion: Key Questions for the Case

• A key evidentiary question will be one of technical applicability: can the plaintiff demonstrate that the architecture of a high-performance workstation, the "Apexx A3," contains a component that functions as the specific "programmable digital circuit block" described in the '330 patent? The significant difference between the accused product category and the patent's focus on cost-sensitive microcontrollers suggests this will be a central point of dispute.
• The case will also likely turn on a question of definitional scope: will the key claim terms "predetermined digital functions" and "dynamically performed" be construed broadly, or will they be limited to the context of real-time, on-the-fly reconfiguration of simple hardware blocks as detailed in the patent's specification and examples? The resolution of this question will be critical in determining whether the functionality of the accused product falls within the scope of the asserted claim.