DCT

6:22-cv-00452

Cedar Lane Tech Inc v. Brickcom Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00452, W.D. Tex., 05/04/2022
  • Venue Allegations: Plaintiff alleges venue is proper because Defendant is a foreign corporation, has committed acts of patent infringement in the district, and has caused harm there.
  • Core Dispute: Plaintiff alleges that Defendant’s imaging and camera products infringe three U.S. patents related to interfacing image sensors with compression hardware and host processor systems.
  • Technical Context: The patents address methods for efficiently managing the flow of digital image data from a sensor to other components for processing, compression, or storage, a foundational technology in digital cameras and scanners.
  • Key Procedural History: The complaint does not mention any prior litigation, IPR proceedings, or licensing history related to the patents-in-suit. U.S. Patent 8,537,242 is a divisional of the application that led to U.S. Patent 6,972,790.

Case Timeline

Date Event
1999-06-01 Priority Date for U.S. Patent No. 6,473,527
2000-01-21 Priority Date for U.S. Patent Nos. 6,972,790 and 8,537,242
2002-10-29 Issue Date for U.S. Patent No. 6,473,527
2005-12-06 Issue Date for U.S. Patent No. 6,972,790
2013-09-17 Issue Date for U.S. Patent No. 8,537,242
2022-05-04 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002

The Invention Explained

  • Problem Addressed: The patent's background section describes that conventional digital imaging systems using JPEG compression often required an "extra memory device," such as external RAM, to act as a buffer between the analog-to-digital (A/D) converter and the dedicated JPEG compression hardware. This extra component added cost and complexity to devices like scanners. (’527 Patent, col. 1:37-57).
  • The Patented Solution: The invention proposes an interface module that sits between the A/D converter and the JPEG compression device. This module contains its own memory, sized specifically to store a predetermined number of image lines (e.g., eight lines) that correspond to the size of a compression unit (e.g., an 8x8 pixel block). This allows the module to receive image data line-by-line and then forward it to the compression device in perfectly sized "image blocks," eliminating the need for the larger, external buffer memory. (’527 Patent, Abstract; col. 2:3-24).
  • Technical Importance: This design aimed to reduce the component count, cost, and complexity of digital imaging products by creating a more efficient data pathway for standardized block-based compression algorithms. (’527 Patent, col. 1:55-57).

Key Claims at a Glance

  • The complaint asserts "one or more claims" of the ’527 Patent without specifying them, incorporating by reference an unfiled exhibit (Compl. ¶13). Independent claim 1 is representative.
  • Independent Claim 1 recites a module comprising:
    • A "read control means" for sequentially reading a predetermined number of image lines from an A/D converter and generating a control signal.
    • A "memory means" for storing those image lines, with a capacity matching the number of lines in the built-in memory of the JPEG compression device.
    • An "output control means" that responds to the control signal by sequentially reading an "image block" from the memory means and forwarding it to the JPEG device's built-in memory.
  • The complaint reserves the right to assert other claims, including dependent claims. (Compl. ¶13).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005

The Invention Explained

  • Problem Addressed: The patent describes a fundamental incompatibility between the continuous, video-style data stream produced by CMOS image sensors and the random-access, bus-based architecture of commercial microprocessors. Bridging this gap required "additional glue logic," which diminished the cost-effectiveness of integrating the sensor and processing logic onto a single chip. (’790 Patent, col. 1:38-54).
  • The Patented Solution: The patent discloses an interface, preferably integrated onto the same semiconductor die as the image sensor, which acts as an intelligent buffer. It receives and stores data from the imaging array in a memory (such as a FIFO buffer) and, in response to the quantity of data stored, generates a signal (e.g., a hardware interrupt) to the main processor system. This signal alerts the processor that data is ready for transfer, which is then managed at a rate determined by the processor system. (’790 Patent, Abstract; col. 2:3-14).
  • Technical Importance: This architecture facilitates the development of more highly integrated "system-on-a-chip" (SoC) imaging devices by embedding the necessary interface logic directly with the sensor, thereby reducing external component count, power consumption, and manufacturing cost. (’790 Patent, col. 1:61-64).

Key Claims at a Glance

  • The complaint asserts "one or more claims" without specification, incorporating by reference an unfiled exhibit (Compl. ¶19). Independent claim 1 is representative.
  • Independent Claim 1 recites an interface for an image sensor comprising:
    • A "memory for storing imaging array data and clocking signals" at a rate determined by those signals.
    • A "signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory."
    • A "circuit for controlling the transfer of the data from the memory" at a rate determined by the processor system.
  • The complaint reserves the right to assert other claims. (Compl. ¶19).

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued September 17, 2013

  • Technology Synopsis: As a divisional of the application that produced the ’790 Patent, this patent covers similar technology. It describes an interface for managing data transfer between an image sensor and a host processor, using a memory buffer to reconcile the different data handling protocols of the two components and using a signaling mechanism to coordinate the transfer. (Compl. ¶11; ’242 Patent, Abstract).
  • Asserted Claims: The complaint asserts "one or more claims" without specification, incorporating by reference an unfiled exhibit. (Compl. ¶28, ¶33). Independent claims 1, 8, 14, and 19 are available for assertion.
  • Accused Features: The complaint alleges that the "Exemplary Defendant Products" infringe by practicing the technology claimed in the patent. (Compl. ¶28).

III. The Accused Instrumentality

  • Product Identification: The complaint refers to "Exemplary Defendant Products" that are identified in claim chart exhibits. (Compl. ¶13, ¶19, ¶28).
  • Functionality and Market Context: The complaint does not provide the referenced exhibits or any other specific details regarding the accused products' names, technical functionality, or market position. Therefore, a specific analysis of the accused instrumentality is not possible based on the provided documents.

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

The complaint incorporates infringement allegations by referencing claim chart exhibits that were not included with the public filing. (Compl. ¶16, ¶25, ¶34). It makes the general assertion that the "Exemplary Defendant Products practice the technology claimed" by the patents-in-suit. (Compl. ¶15, ¶24, ¶33). In the absence of detailed charts, a summary of the narrative infringement theory is provided below.

’527 Patent Infringement Allegations

The complaint alleges that Defendant's products infringe by including a module or method that interfaces an A/D converter with a JPEG compression means in a manner that satisfies all limitations of the asserted claims. (Compl. ¶13, ¶15). This suggests the products contain distinct functional blocks corresponding to the claimed "read control means," "memory means," and "output control means."

  • Identified Points of Contention:
    • Structural Questions: A potential dispute may arise over whether the accused products contain three distinct structural or logical components that map directly onto the three "means" elements of Claim 1, or if a single, more integrated component performs the claimed functions.
    • Functional Questions: The case may turn on whether the accused products' memory management operates as claimed—specifically, by storing a "predetermined number of image lines" and then forwarding a discrete "image block" to a compression device.

’790 Patent Infringement Allegations

The complaint alleges that Defendant's products infringe by including a host interface for an imaging array that practices the claimed invention. (Compl. ¶19, ¶24). The core of this allegation is that the products use a memory buffer and a signaling protocol to manage the transfer of image data from a sensor to a processor system.

  • Identified Points of Contention:
    • Scope Questions: A central question may be what constitutes a "signal... in response to the quantity of data in the memory." The parties may dispute whether this requires the signal to be triggered by a specific data threshold (e.g., buffer is 75% full), as suggested by the specification, or if a signal triggered by other events (e.g., end of frame) meets the limitation.
    • Technical Questions: Evidence will be needed to determine how the data transfer rate is controlled. A key issue will be whether the rate is "determined by the processor system," as claimed, or if it is dictated by the sensor or another component.

V. Key Claim Terms for Construction

For the ’527 Patent

  • The Term: "image block" (from Claim 1)
  • Context and Importance: The claim requires the output control means to read and forward an "image block." The definition of this term is critical to determining if the data chunking and formatting in an accused device matches the specific process claimed by the patent. Practitioners may focus on this term to determine if it is limited to the specific format required by a compression algorithm like JPEG.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term itself is not explicitly defined in the claim, which could support an interpretation covering any discrete segment of image data transferred from the buffer.
    • Evidence for a Narrower Interpretation: The specification consistently provides the example of an "image block of 8x8 pixels" as the "basic compression unit" for a "general JPEG compression algorithm." (’527 Patent, col. 1:43-45). This linkage could support an argument that "image block" is not just any data segment, but one sized specifically for the downstream compression device.

For the ’790 Patent

  • The Term: "in response to the quantity of data in the memory" (from Claim 1)
  • Context and Importance: This phrase defines the trigger for the "signal generator." Its construction is central to the infringement analysis, as it dictates the required causal relationship between the buffer's state and the signal sent to the processor. The case may depend on whether an accused device's signaling protocol meets this requirement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: A party might argue that any signal generated after some data has been stored in memory (a "quantity") meets this limitation, even if the trigger is not a specific fill level.
    • Evidence for a Narrower Interpretation: The detailed description teaches an embodiment where an interrupt is generated by comparing a "FIFO counter output" (Sc) to a "FIFO limit" (Sʟ), indicating the signal is generated when the quantity of data reaches a specific, predetermined level. (’790 Patent, col. 6:11-14). This may support a narrower construction requiring a threshold-based trigger.

VI. Other Allegations

  • Indirect Infringement: For the ’790 and ’242 Patents, the complaint alleges induced infringement. The stated basis for inducement is that Defendant allegedly distributes "product literature and website materials" that instruct end users on how to use the accused products in a manner that infringes the patents. (Compl. ¶22-¶23, ¶31-¶32).
  • Willful Infringement: The complaint alleges that Defendant had "actual knowledge" of the ’790 and ’242 Patents at least as of the service of the complaint. It alleges that any continued infringement after this date is willful. (Compl. ¶21-¶22, ¶30-¶31). The prayer for relief requests enhanced damages for all three patents. (Compl., Prayer for Relief ¶H, ¶I).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. A primary issue will be evidentiary and factual: Given the complaint's lack of specific product details and its reliance on unfiled exhibits, the case will depend entirely on whether discovery reveals that Defendant's products contain the specific hardware and software architectures—including the control logic, memory management, and signaling protocols—recited in the asserted claims.
  2. A second issue will be one of claim scope and technical operation: For the ’527 patent, does the accused system's data handling constitute forwarding a discrete "image block" whose size is tied to a compression unit, as the specification suggests? For the ’790 and ’242 patents, does the accused interface’s signaling mechanism operate "in response to the quantity of data in the memory" in the specific threshold-based manner described in the patent, or does it employ a different triggering logic that may fall outside the scope of the claims?
  3. A final question relates to indirect infringement: Can the plaintiff demonstrate that Defendant's product literature and manuals actively instruct or encourage users to configure or operate the accused products in a way that directly satisfies all elements of a claimed method or system, thereby establishing the requisite intent for inducement?