DCT

6:22-cv-00669

InnoMemory LLC v. Rubric Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-00669, W.D. Tex., 06/24/2022
  • Venue Allegations: Plaintiff alleges venue is proper based on Defendant maintaining a regular and established place of business in the Western District of Texas and committing alleged acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s use of computing devices incorporating industry-standard DDR memory infringes patents related to high-performance memory architecture and power-saving techniques for refresh operations.
  • Technical Context: The technology concerns methods for improving the efficiency of Dynamic Random-Access Memory (DRAM) by balancing data access speed with power consumption, a critical design consideration for all modern computing systems.
  • Key Procedural History: The complaint is an initial pleading and does not mention prior litigation, licensing history, or administrative patent challenges. The infringement allegations are based on the functionality of memory devices that comply with JEDEC industry standards. Plaintiff expressly reserves the right to amend the complaint to add allegations of indirect and willful infringement should discovery reveal pre-suit knowledge by the Defendant.

Case Timeline

Date Event
1999-02-13 ’046 Patent Priority Date
2001-05-29 ’046 Patent Issue Date
2002-03-04 ’960 Patent Priority Date
2006-06-06 ’960 Patent Issue Date
2022-06-24 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,240,046 - "INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE"

The Invention Explained

  • Problem Addressed: The patent describes a need for memory devices with low power consumption, particularly for portable computing systems. Prior art memory devices were often inefficient, either by retrieving only one data word per memory access cycle or by retrieving multiple data words and discarding unused ones, which wastes power. (’046 Patent, col. 2:1-15).
  • The Patented Solution: The invention is a random access memory architecture capable of operating in different modes to conserve power. It can retrieve a single data word in a clock cycle for random read requests, or it can retrieve more than one data word in a single clock cycle for burst requests, which reduces the number of times the memory array must be accessed for sequential data. (’046 Patent, Abstract; col. 2:20-29). The state of the memory can be controlled by a flip-flop to switch between single-word and multi-word retrieval modes. (’046 Patent, col. 2:45-46).
  • Technical Importance: This flexible architecture sought to optimize memory operation by balancing the competing demands of high performance for sequential data access and low power consumption for random data access. (’046 Patent, col. 2:11-15).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2-19. (Compl. ¶12).
  • Independent Claim 1 includes the following essential elements:
    • An integrated circuit random access memory
    • Comprising a memory array for storing a plurality of data words
    • And a data bus coupled to the memory array for conveying data words retrieved from the memory array
    • The data bus having a width of more than one data word
    • Wherein the integrated circuit random access memory retrieves more than one data word from the memory array in a single clock cycle.

U.S. Patent No. 7,057,960 - "METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS"

The Invention Explained

  • Problem Addressed: The patent background explains that conventional Dynamic Random Access Memories (DRAMs) consume significant power in standby mode because they must periodically refresh all memory cells to retain data. This is inefficient for applications, such as battery-powered devices, that may only need to preserve data in a small portion of the total memory. (’960 Patent, col. 1:25-40).
  • The Patented Solution: The invention proposes a method and architecture for reducing power consumption by dividing the memory array into multiple sections. The background operations, particularly refresh operations, can be controlled to occur in only a subset of these sections. (’960 Patent, Abstract). By presenting control and address signals only to the periphery circuits of the sections being refreshed, the power consumed by refreshing inactive sections is eliminated. (’960 Patent, col. 2:37-56).
  • Technical Importance: This selective, or partial-array, refresh capability allows for more granular power management in memory devices, a key feature for extending battery life in mobile electronics. (’960 Patent, col. 1:33-40).

Key Claims at a Glance

  • The complaint asserts independent claim 1 and dependent claims 2-27. (Compl. ¶20).
  • Independent Claim 1 recites a method with the following essential steps:
    • A method for reducing power consumption during background operations in a memory array with a plurality of sections
    • Controlling said background operations in each of said plurality of sections in response to one or more control signals,
    • Wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
    • Presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.

III. The Accused Instrumentality

Product Identification

The complaint broadly accuses "Accused DDR Memory" and "Accused Computing Device[s]" used by Defendant Rubric Inc. (Compl. ¶8, 10). The accused memory is defined as any device that complies with JEDEC industry standards including DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5. (Compl. ¶8, 16). The accused computing devices are identified as products that incorporate this memory, with the complaint listing servers, desktops, laptops, and automated teller machines as examples of devices Rubrik has allegedly "owned and operated." (Compl. ¶12, 20-23).

Functionality and Market Context

The complaint does not describe the specific functionality of Rubrik's products or services. Instead, it alleges infringement based on the functionality mandated by the JEDEC standards for DDR memory. (Compl. ¶9, 17). The complaint alleges that Rubrik uses devices containing the accused memory and sells products and services throughout Texas. (Compl. ¶2). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint references exemplary claim charts (Exhibits A and B) that allegedly map claims of the patents-in-suit to industry standards like the DDR4 technical specification. (Compl. ¶9, 17). As these exhibits were not included with the filed complaint, the infringement theory is summarized below in prose.

’046 Patent Infringement Allegations

The complaint alleges that any memory device compliant with the specified DDR standards infringes one or more of claims 1-19 of the ’046 Patent. (Compl. ¶8, 12). The theory of infringement appears to be that the mandatory burst-read capabilities inherent in these standards satisfy the claim limitations. Specifically, the standards-based functionality of retrieving multiple data words in response to a single read command is alleged to meet the claim requirement of retrieving "more than one data word from the memory array in a single clock cycle." (Compl. ¶9).

’960 Patent Infringement Allegations

The complaint alleges that memory devices compliant with the same DDR standards also infringe one or more of claims 1-27 of the ’960 Patent. (Compl. ¶16, 20). The infringement theory appears to be based on power-saving features in the standards, such as Partial-Array Self-Refresh (PASR), which allows a memory device to refresh only a portion of its memory array. This functionality is alleged to meet the claim limitations of controlling background (refresh) operations in a subset of memory sections in response to control signals to reduce power consumption. (Compl. ¶17).

  • Identified Points of Contention:
    • Scope Questions: A central question will be whether the functionality mandated by the JEDEC standards is coextensive with the scope of the patent claims. For the ’046 Patent, this raises the question of whether a standard "burst read" is technically and legally equivalent to retrieving multiple data words "in a single clock cycle" as that term is construed from the patent's specification.
    • Technical Questions: For the ’960 Patent, a key technical question is whether the implementation of power-saving features like PASR in the accused standards operates in a manner that meets all limitations of the asserted claims. For example, what evidence does the complaint provide that the standard-compliant devices perform refresh operations in multiple sections "simultaneously" and "independently of any other section" as required by claim 1? The complaint's reliance on unprovided exhibits leaves these factual underpinnings unstated in the pleading.

V. Key Claim Terms for Construction

  • The Term: "in a single clock cycle" (from ’046 Patent, Claim 1)

  • Context and Importance: This term defines the temporal scope of the multi-word retrieval action. Its construction will be critical because modern Double Data Rate (DDR) memory transfers data on both the rising and falling edges of a clock signal. Practitioners may focus on whether this two-part transfer process constitutes retrieval "in a single clock cycle" as understood at the time the patent was filed.

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The specification describes retrieving "two 36-bit words... in the first cycle" of a burst, suggesting the inventor contemplated retrieving multiple distinct words within one cycle period. (’046 Patent, col. 2:37-38).
    • Evidence for a Narrower Interpretation: The detailed description of some embodiments focuses on accessing the memory array a single time to retrieve multiple words. (’046 Patent, col. 3:1-5). Language describing a single memory array access could be used to argue for a narrower definition that does not cover the distinct data transfer events of DDR technology.

  • The Term: "background operations" (from ’960 Patent, Claim 1)

  • Context and Importance: The asserted method claim is directed to reducing power during "background operations." The patent’s specification primarily discusses "refresh operations" as the target of the invention. Practitioners may focus on this term to dispute whether the accused power-saving modes in the DDR standards qualify as the claimed "background operations."

  • Intrinsic Evidence for Interpretation:

    • Evidence for a Broader Interpretation: The patent's abstract and summary use the general term "background operations," which could support a construction that is not strictly limited to memory refresh. (’960 Patent, Abstract; col. 2:38-39).
    • Evidence for a Narrower Interpretation: The "Background of the Invention" section frames the technical problem almost exclusively in terms of power consumed by "periodic refresh" operations in DRAMs. (’960 Patent, col. 1:13-24). This context may support a narrower construction limited to the types of refresh operations described.

VI. Other Allegations

  • Indirect Infringement: The complaint does not currently plead induced or contributory infringement. It reserves the right to add such claims pending discovery. (Compl. ¶9 n.1, ¶17 n.3).
  • Willful Infringement: The complaint does not currently plead willful infringement. It reserves the right to add a willfulness claim if discovery reveals pre-suit knowledge of the patents-in-suit. (Compl. ¶9 n.1, ¶17 n.3).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Standards vs. Claim Scope: A central issue will be whether compliance with the JEDEC DDR standards is sufficient to prove infringement. The case may turn on a detailed comparison between the claim language, as construed by the court, and the mandatory functions of the standards, raising the question of whether infringement can be established by demonstrating standards-compliance alone.
  2. Temporal Construction: For the ’046 patent, a key question will be one of definitional scope: can the term “in a single clock cycle,” which originates from a patent filed in 2000, be construed to cover modern Double Data Rate memory architectures that transfer data on both the rising and falling edges of the clock signal?
  3. Operational Equivalence: For the ’960 patent, a key evidentiary question will be whether the accused power-saving modes in DDR standards, such as Partial-Array Self-Refresh, function in a manner that meets the claim requirement of independently and simultaneously controlling background operations across multiple memory sections.