DCT
6:22-cv-00671
InnoMemory LLC v. USAA Federal Savings Bank
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Innomemory, LLC (Texas)
- Defendant: USAA Federal Savings Bank. (Texas)
- Plaintiff’s Counsel: Ramey LLP
- Case Identification: 6:22-cv-00671, W.D. Tex., 06/24/2022
- Venue Allegations: Plaintiff alleges venue is proper because Defendant is a Texas financial institution with regular and established places of business in the Western District of Texas where it allegedly uses the infringing devices.
- Core Dispute: Plaintiff alleges that Defendant’s use of computing devices containing industry-standard DDR memory infringes patents related to power-saving methods for memory read and refresh operations.
- Technical Context: The patents address methods for reducing power consumption in Dynamic Random-Access Memory (DRAM), a critical technology for everything from large servers to portable electronics.
- Key Procedural History: The complaint does not mention any prior litigation, IPR proceedings, or licensing history related to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 1999-02-13 | ’046 Patent Priority Date |
| 2001-05-29 | ’046 Patent Issue Date |
| 2002-03-04 | ’960 Patent Priority Date |
| 2006-06-06 | ’960 Patent Issue Date |
| 2022-06-24 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,240,046 - "INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE"
The Invention Explained
- Problem Addressed: The patent describes a power consumption problem in prior art memory devices. Some devices retrieve multiple data words in a single read cycle even when only one is needed, wasting power by accessing and then discarding the unrequested data. This is particularly inefficient in portable computing systems where power conservation is critical (’046 Patent, col. 2:3-15).
- The Patented Solution: The invention is a random access memory circuit designed to save power by adapting its read operation to the type of request. It can operate in two modes: for random, non-sequential read requests, it retrieves only a single data word in a clock cycle; for sequential "burst" requests, it retrieves more than one data word in a clock cycle, which is more efficient for that specific task (’046 Patent, col. 2:20-32; Abstract). This dual-mode capability is intended to lower the average power consumption across different use cases (’046 Patent, col. 2:58-64).
- Technical Importance: This approach addresses the trade-off between speed and power efficiency by allowing memory to dynamically select the more power-efficient retrieval method based on the nature of the memory access request (’046 Patent, col. 2:11-15).
Key Claims at a Glance
- The complaint asserts independent claim 1 and dependent claims 2-19 (’046 Patent, col. 12:5-13:17; Compl. ¶12).
- Independent Claim 1 requires:
- A memory array capable of storing a plurality of data words.
- A data bus coupled to the memory array, having a width of more than one data word.
- Wherein the circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle immediately following the first.
U.S. Patent No. 7,057,960 - "METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS"
The Invention Explained
- Problem Addressed: The patent notes that conventional DRAMs must periodically refresh all memory cells to prevent data loss, even when the device is in a low-power standby mode. For applications like mobile terminals, which may only need to retain data in a small portion of the total memory, refreshing the entire array is a significant and unnecessary power drain (’960 Patent, col. 1:36-51).
- The Patented Solution: The invention proposes a memory architecture divided into multiple sections, where background operations like "refresh" can be controlled independently for each section. This allows the system to activate the support circuitry only for the sections containing data that needs to be preserved, while leaving the circuitry for other sections inactive, thereby reducing overall power consumption in standby mode (’960 Patent, Abstract; col. 2:35-44).
- Technical Importance: This sectional refresh capability allows for more granular power management in memory devices, a key requirement for extending battery life in portable electronics (’960 Patent, col. 1:40-44).
Key Claims at a Glance
- The complaint asserts independent claims 1 and 9, and dependent claims 2-8 and 10-27 (’960 Patent, col. 8:40-10:29; Compl. ¶20).
- Independent Claim 1 recites a method comprising:
- Controlling background operations in each of a plurality of sections of a memory array in response to one or more control signals.
- Wherein the control signals are generated in response to a programmable address signal.
- Wherein the background operations can be enabled simultaneously in two or more sections independently of any other section.
- Presenting the control signals and decoded address signals to periphery array circuits of the sections.
III. The Accused Instrumentality
Product Identification
The complaint identifies the accused instrumentalities as "Accused Computing Device[s]" owned and operated by Defendant USAA, including servers, desktop computers, laptops, tablets, and automated teller machines (ATMs) (Compl. ¶10, ¶18, ¶21-23). These devices are accused of infringement because they contain "Accused DDR Memory" (Compl. ¶10).
Functionality and Market Context
- The complaint alleges that the "Accused DDR Memory" includes any memory device that complies with industry standards such as DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5 (Compl. ¶8, ¶16).
- The infringement theory is predicated on the allegation that compliance with these JEDEC standards inherently requires practicing the patented technologies (Compl. ¶9, ¶17). The complaint does not describe the specific functionality of the accused products beyond their alleged compliance with these standards.
- No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint references exemplary claim chart exhibits (Exhibits A, B-E) that are not provided. The following summary is based on the narrative allegations in the complaint body.
’046 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a memory array capable of storing a plurality of data words; | The Accused DDR Memory is alleged to contain a memory array for storing data. | ¶8, ¶10 | col. 1:22-25 |
| a data bus coupled to the memory array, the data bus having a width of more than one data word; | The Accused DDR Memory is alleged to operate with a multi-word data bus, consistent with DDR standards. | ¶8, ¶12 | col. 2:23-25 |
| wherein the random access memory integrated circuit is capable of retrieving a first data word from the memory array in a first clock cycle and a second data word from the memory array in a second clock cycle... | The Accused DDR Memory is alleged to perform multi-word read operations consistent with DDR standards. | ¶8, ¶12 | col. 2:25-29 |
Identified Points of Contention:
- Scope Questions: A central question may be whether the general capability of DDR memory to perform both single-word and burst-mode reads is sufficient to meet the specific claim limitations. The patent describes a particular architecture for achieving this dual-mode capability, and the analysis will likely focus on whether the accused products use that same architecture.
- Technical Questions: What evidence does the complaint provide that standard-compliant DDR memory necessarily practices the method of retrieving data words in distinct, immediately sequential clock cycles as claimed? The complaint's reliance on industry standards raises the question of whether every implementation of those standards practices the claimed invention, or only some.
’960 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| controlling said background operations in each of said plurality of sections of said memory array... | The Accused DDR Memory is alleged to perform background operations, such as refresh, on a sectional basis. | ¶16, ¶20 | col. 2:37-41 |
| ...in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal... | The complaint alleges that DDR memory that complies with certain industry standards necessarily uses control signals generated from a programmable address to manage sectional background operations. | ¶16, ¶17, ¶20 | col. 8:44-49 |
| ...and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section... | The complaint's theory suggests that standard-compliant DDR memory allows for independent and simultaneous background operations in multiple memory sections. | ¶16, ¶17, ¶20 | col. 8:49-52 |
Identified Points of Contention:
- Scope Questions: The analysis will likely focus on whether the term "programmable address signal" as used in the patent reads on the mechanisms used in DDR standards to control partial-array refresh operations. The defense may argue for a narrower construction tied to the patent's specific embodiments.
- Technical Questions: Does the complaint provide sufficient detail to establish how the power-saving modes in standard DDR memory (e.g., Partial Array Self-Refresh in LPDDR) function, and whether that functionality maps onto every element of the asserted claims? The dispute may turn on the specific implementation of refresh control in the accused memory chips versus the method described in the patent.
V. Key Claim Terms for Construction
The complaint does not provide sufficient detail for analysis of specific claim terms. However, based on the technology and the nature of the allegations, certain terms may become central to the dispute.
The Term: "flip-flop" (’046 Patent, Claim 5)
Context and Importance: While this term appears in a dependent claim, the complaint asserts claims 1-19, and the specification heavily features a flip-flop as the mechanism for switching between single-word and multi-word read modes (’046 Patent, col. 2:45-46). Practitioners may focus on this term because its construction could be critical to distinguishing the patented invention from the way accused DDR products manage burst mode operations, which may or may not use a structure that meets the definition of a "flip-flop."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states that some embodiments "can include a flip-flop having a first state and a second state," which may suggest it is one possible implementation rather than a strict requirement for the broader invention (’046 Patent, col. 2:45-46).
- Evidence for a Narrower Interpretation: The detailed description consistently describes the flip-flop as the control element that toggles between the power-saving single-read mode and the multi-read burst mode, suggesting its structural and functional role is integral to the invention as disclosed (’046 Patent, col. 3:33-43).
The Term: "controlling said background operations ... in response to one or more control signals" (’960 Patent, Claim 1)
Context and Importance: This term is central to how the patented method is implemented. The dispute will likely involve whether the specific signals and control logic used in standard DDR memory for partial refresh fall within the scope of this claim language.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim uses the general term "control signals," which could be argued to encompass any signal that directs the sectional refresh, including those defined by the JEDEC standards. The patent states the invention concerns a "method for reducing power consumption during background operations," suggesting a focus on the functional outcome (’960 Patent, col. 2:35-37).
- Evidence for a Narrower Interpretation: The specification describes presenting "one or more control signals and one or more decoded address signals to one or more periphery array circuits" (’960 Patent, Abstract). A defendant may argue this requires a specific type of control architecture where decoded addresses directly gate control signals to peripheral circuits, potentially distinguishing it from the accused DDR memory architecture.
VI. Other Allegations
- Indirect Infringement: The complaint does not currently allege indirect infringement but explicitly "reserves the right to amend" to add such claims if discovery reveals the requisite knowledge (Compl. p. 3 n.1, p. 4 n.2, p. 4 n.3, p. 5 n.4).
- Willful Infringement: The complaint does not currently allege willful infringement but makes the same reservation to add such a claim upon discovery of pre-suit knowledge (Compl. p. 3 n.1, p. 4 n.2, p. 4 n.3, p. 5 n.4).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of standards versus infringement: can the Plaintiff demonstrate that mere compliance with the cited JEDEC DDR standards necessarily results in a memory architecture that practices every limitation of the asserted claims, or will the Defendant be able to show that the standards can be implemented in non-infringing ways?
- A key evidentiary question will be one of technical mapping: does the specific circuitry and control logic used in the Accused DDR Memory for managing burst-mode reads and partial-array refresh operations align with the specific architectures described and claimed in the ’046 and ’960 patents, or is there a fundamental mismatch in technical operation? The high-level nature of the complaint leaves this as a primary question for discovery and expert testimony.