DCT
6:22-cv-00672
InnoMemory LLC v. Cullen Frost Bankers Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Innomemory, LLC (Texas)
- Defendant: Cullen/Frost Bankers, Inc. (Texas)
- Plaintiff’s Counsel: Ramey LLP
- Case Identification: 6:22-cv-00672, W.D. Tex., 10/13/2022
- Venue Allegations: Plaintiff alleges venue is proper based on Defendant having regular and established places of business within the Western District of Texas and committing alleged acts of infringement in the district.
- Core Dispute: Plaintiff alleges that Defendant’s use of computing devices, including ATMs and mainframes containing industry-standard DDR memory, infringes patents related to methods for memory circuit operation and power consumption.
- Technical Context: The technology at issue is Double Data Rate (DDR) synchronous dynamic random-access memory, a ubiquitous and fundamental component in modern computing that enables high-speed data storage and retrieval.
- Key Procedural History: The operative pleading is the Plaintiff’s Second Amended Complaint, which was authorized by a Court Order dated September 30, 2022.
Case Timeline
| Date | Event |
|---|---|
| 1999-02-13 | U.S. Patent No. 6,240,046 Priority Date |
| 2001-05-29 | U.S. Patent No. 6,240,046 Issue Date |
| 2001-06-25 | Date of article cited as evidence of Defendant's laptop use |
| 2002-03-04 | U.S. Patent No. 7,057,960 Priority Date |
| 2006-06-06 | U.S. Patent No. 7,057,960 Issue Date |
| 2022-09-30 | Court Order authorizing Second Amended Complaint |
| 2022-10-13 | Second Amended Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,240,046 - “INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE”
- Patent Identification: U.S. Patent No. 6,240,046, “INTEGRATED CIRCUIT RANDOM ACCESS MEMORY CAPABLE OF READING EITHER ONE OR MORE THAN ONE DATA WORD IN A SINGLE CLOCK CYCLE,” issued May 29, 2001.
The Invention Explained
- Problem Addressed: The patent’s background section describes a need for memory devices with low power consumption characteristics suitable for varied environments, such as portable computing systems. It notes that prior art memories were often optimized for either random read requests (retrieving one data word at a time) or burst read requests (retrieving multiple words), leading to inefficient power usage when the access pattern did not match the memory’s design (ʼ046 Patent, col. 2:1-15).
- The Patented Solution: The invention is a random access memory circuit capable of operating in different modes. It can retrieve a single data word from the memory array in one clock cycle for random memory reads, or it can retrieve more than one data word in a single clock cycle for burst requests. This adaptability claims to save power by matching the memory access strategy to the type of read request being performed (ʼ046 Patent, Abstract; col. 2:45-56).
- Technical Importance: This approach provided a method to optimize power consumption in memory systems that handle both random and sequential data access patterns, a common scenario in devices ranging from portable computers to high-performance servers (ʼ046 Patent, col. 2:11-15).
Key Claims at a Glance
The complaint alleges infringement of "one or more method claims" but does not identify specific claims (Compl. ¶13). The following analysis is based on independent method claim 9 as a representative example.
- Independent Claim 9:
- retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations; and
- retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations.
- The complaint reserves the right to amend and add claims for indirect and willful infringement pending discovery (Compl. ¶14, fn. 6).
U.S. Patent No. 7,057,960 - “METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS”
- Patent Identification: U.S. Patent No. 7,057,960, “METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS,” issued June 6, 2006.
The Invention Explained
- Problem Addressed: The patent’s background section states that conventional Dynamic Random Access Memories (DRAMs) typically refresh all memory cells to maintain data integrity. This process consumes power even in standby mode, which is detrimental for battery-powered portable devices where only a portion of the memory may need to be retained (ʼ960 Patent, col. 1:36-54).
- The Patented Solution: The invention describes a method for reducing power consumption by controlling background operations, such as refresh, in discrete sections of a memory array. By activating the periphery array circuits for only the sections that require refreshing and leaving others inactive, the system can reduce standby power usage ('960 Patent, Abstract; col. 2:37-44).
- Technical Importance: This selective refresh capability was designed to extend battery life in mobile terminals and other portable appliances by minimizing power consumption during standby periods when full memory retention is not required ('960 Patent, col. 2:29-35).
Key Claims at a Glance
The complaint alleges infringement of "one or more method claims" but does not specify which ones (Compl. ¶22). The following analysis is based on independent method claim 1 as a representative example.
- Independent Claim 1:
- controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section; and
- presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections.
- The complaint reserves the right to amend and add claims for indirect and willful infringement pending discovery (Compl. ¶19, fn. 7).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Instrumentalities" as computing devices used by Defendant that contain "Accused DDR Memory" (Compl. ¶9, 11). This memory is defined as any device compliant with JEDEC industry standards including DDR2, DDR3, DDR4, LPDDR3, LPDDR4, LPDDR4X, and LPDDR5 (Compl. ¶8, 17). Specific instrumentalities named include NCR SelfServ model 22 and Diebold Opteva 522 ATM machines, as well as IBM Z13 and Z14 series mainframe computers (Compl. ¶9, 18).
Functionality and Market Context
- Defendant Cullen/Frost Bankers, Inc. ("Frost") is alleged to use these instrumentalities in its banking operations throughout Texas (Compl. ¶2). The complaint provides photographic evidence of Frost-branded ATMs deployed in public locations, such as an image of an ATM at a San Antonio Circle K Store (Compl. p. 4). The Accused DDR Memory within these devices performs standard high-speed data storage and retrieval functions necessary for the operation of the ATMs and servers (Compl. ¶8, 9).
- The complaint alleges that Frost has used these instrumentalities, which incorporate the Accused DDR Memory, during the damages period of the patents-in-suit (Compl. ¶9).
IV. Analysis of Infringement Allegations
The complaint references claim-chart exhibits (Exhibits A-D) that are not provided with the filed document (Compl. ¶10, 19). The following analysis is based on the narrative infringement theory presented in the complaint, which alleges that compliance with certain JEDEC industry standards constitutes infringement of the asserted patents.
'046 Patent Infringement Allegations
| Claim Element (from Independent Claim 9) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| retrieving one of a plurality of data words from the memory array in a read clock cycle when addressing separate single unrelated memory locations | Accused DDR Memory, by complying with JEDEC standards (e.g., DDR3, DDR4), performs single data word read operations in response to random memory access requests. | ¶8, 10, 13 | col. 9:56-60 |
| retrieving more than one data words from the memory array in the read clock cycle when accessing bursts of related memory locations | Accused DDR Memory, by complying with JEDEC standards (e.g., DDR3, DDR4), performs multi-word burst read operations to retrieve sequential data. | ¶8, 10, 13 | col. 9:60-64 |
'960 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| controlling said background operations in each of said plurality of sections of said memory array in response to one or more control signals, wherein said one or more control signals are generated in response to a programmable address signal... | Accused DDR Memory, compliant with JEDEC standards, allegedly utilizes control signals and programmable addresses to manage background operations like self-refresh on a sectional (e.g., per-bank) basis. | ¶17, 19, 22 | col. 8:38-44 |
| ...and said background operations can be enabled simultaneously in two or more of said plurality of sections independently of any other section... | The complaint's theory suggests that features within the accused JEDEC standards, such as partial array self-refresh (PASR), allow for the independent control and simultaneous enabling of refresh operations across different memory sections. | ¶17, 19, 22 | col. 9:16-20 |
| presenting said one or more control signals and one or more decoded address signals to one or more periphery array circuits of said plurality of sections. | Accused DDR Memory allegedly uses control and address signals to activate the necessary support circuitry (periphery array circuits) for only those sections of the memory array undergoing a background operation. | ¶17, 19, 22 | col. 8:44-48 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the defendant’s end-use of commercially available computing equipment constitutes direct infringement of the asserted method claims. The dispute may focus on whether the user of a product "practices" the methods claimed for the internal operation of a component within that product.
- Technical Questions: The complaint's infringement theory appears to rest on the assertion that compliance with a JEDEC standard is sufficient to establish that a device performs the claimed methods. A point of contention may be what evidence the complaint provides that the features of the DDR standards (e.g., burst mode, self-refresh) perform the specific, multi-part functions required by the claims of the ʼ046 and ʼ960 patents.
V. Key Claim Terms for Construction
- The Term: "retrieving...in a read clock cycle" (’046 Patent, Claim 9)
- Context and Importance: The definition of this term is critical because infringement hinges on whether the standard operation of Accused DDR Memory constitutes "retrieving" data in the manner and timing context described by the patent. Practitioners may focus on whether this term requires a specific mode-switching capability, as described in the specification, or if it more broadly covers any memory that can perform both single and burst reads.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language is broad, referring to two distinct types of retrieval without explicitly requiring a single, switchable apparatus. The specification describes the problem in general terms of accessing data words ('046 Patent, col. 2:1-10).
- Evidence for a Narrower Interpretation: The abstract and summary describe an integrated circuit that is "capable of retrieving...either one...or more than one" word, and some embodiments include a flip-flop to select the mode ('046 Patent, Abstract; col. 2:45-47). This may support an interpretation that the "retrieving" methods are tied to a device with this specific dual-mode architecture.
- The Term: "background operations" (’960 Patent, Claim 1)
- Context and Importance: This term's scope will define what functionalities of the accused DDR memory are relevant. The case may turn on whether "background operations" is limited to the "refresh operations" discussed extensively in the patent, or if it also covers other internal memory maintenance functions specified in DDR standards.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim itself uses the general term "background operations" without limitation to refresh. The abstract also refers generally to "background operations in a memory array" ('960 Patent, Abstract).
- Evidence for a Narrower Interpretation: The patent’s title is “METHOD AND ARCHITECTURE FOR REDUCING THE POWER CONSUMPTION FOR MEMORY DEVICES IN REFRESH OPERATIONS.” The background and summary sections focus almost exclusively on "refresh" as the power-consuming operation to be optimized, which could support limiting the claim term to that context ('960 Patent, Title; col. 1:16-19).
VI. Other Allegations
- Indirect Infringement: The complaint makes no factual allegations to support claims of induced or contributory infringement but reserves the right to add such claims if discovery reveals pre-suit knowledge by the Defendant (Compl. ¶14, fn. 6; ¶19, fn. 7).
- Willful Infringement: The complaint does not allege willful infringement but reserves the right to amend the complaint to add such claims upon discovery of pre-suit knowledge (Compl. ¶14, fn. 6; ¶19, fn. 7).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of infringement by standard: can the plaintiff demonstrate that mere compliance with the accused JEDEC DDR standards necessarily means that a device practices every limitation of the asserted method claims, or will proving infringement require a more detailed technical analysis of the specific memory chips used by the defendant?
- A key legal question will be one of direct liability for use: does an end-user's operation of standard computing equipment containing DDR memory constitute "practicing" the patented methods, which are directed to the internal operations and power management of the memory circuit itself? The case may explore the division of liability between component manufacturers, system integrators, and end-users.