Cedar Lane Tech Inc v. Matrix Comsec Pvt Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Matrix Comsec Pvt. Ltd. (India)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-00685, W.D. Tex., 06/27/2022
• Venue Allegations: Venue is asserted on the basis that the Defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant’s products infringe three patents related to methods and modules for interfacing image sensors with compression hardware and host processors.
• Technical Context: The technology concerns the efficient management of data transfer between image capture components (like CMOS sensors) and processing systems, a critical function in devices such as digital cameras and scanners.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued October 29, 2002

The Invention Explained

• Problem Addressed: The patent's background describes a problem in prior art image compression systems where an extra, external memory device (typically RAM) was required to buffer image data between an analog-to-digital (A/D) converter and a JPEG compression integrated circuit. This extra component added to the system's cost and complexity (’527 Patent, col. 1:48-57).
• The Patented Solution: The invention proposes an interface module that eliminates the need for this extra memory by managing the data flow more efficiently. The module’s read control device reads a predetermined number of image lines (e.g., 8 lines) into its own memory device, which is sized to match the compression unit of the JPEG device (e.g., an 8x8 pixel block). The module's output control device then feeds these correctly-sized image blocks directly to the JPEG compression device, avoiding the need for a separate, intermediate buffer RAM (’527 Patent, Abstract; col. 2:50-63).
• Technical Importance: This memory management approach was designed to reduce hardware costs and design complexity in image processing devices like scanners and digital cameras by omitting a previously necessary component (’527 Patent, col. 2:21-24).

Key Claims at a Glance

• The complaint does not specify asserted claims, instead incorporating them by reference from an unprovided exhibit (Compl. ¶15). The following analysis is based on independent claim 1 as a representative example.
• Independent Claim 1 of the ’527 Patent recites:
  • A module for interfacing an analog/digital converting means and a JPEG compression means with a built-in memory device.
  • "read control means" for sequentially reading a predetermined number of image lines from the A/D converter and generating a control signal.
  • "memory means" coupled to the read control means for storing the image lines, with a capacity for the same number of lines as the JPEG's built-in memory.
  • "output control means" that responds to the control signal to sequentially read an image block from the memory means and forward it to the JPEG's built-in memory device.
• The complaint reserves the right to assert other claims, which may include dependent claims (Compl. ¶13).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued December 6, 2005

The Invention Explained

• Problem Addressed: The patent addresses the incompatibility between the "video style output" of CMOS image sensors and the data interfaces of commercial microprocessors. This mismatch historically required "additional glue logic" to bridge the two components, diminishing the cost and integration benefits of using CMOS technology (’790 Patent, col. 1:47-53).
• The Patented Solution: The invention describes an interface, preferably integrated onto the same semiconductor die as the image sensor, that manages the asynchronous data transfer between the sensor and a host processor system. The interface uses a memory (such as a FIFO buffer) to store image data arriving at the sensor's clock rate. In response to the quantity of data stored in the memory, a signal generator alerts the processor (e.g., via an interrupt), which can then retrieve the data from the memory at its own rate (’790 Patent, Abstract; col. 2:4-13).
• Technical Importance: By integrating this interface circuitry onto the same chip as the sensor, the invention aimed to fully realize the cost and efficiency advantages of CMOS technology in imaging systems (’790 Patent, col. 2:25-30).

Key Claims at a Glance

• The complaint does not specify asserted claims, instead incorporating them by reference from an unprovided exhibit (Compl. ¶24). The following analysis is based on independent claim 1 as a representative example.
• Independent Claim 1 of the ’790 Patent recites:
  • An interface for receiving data from an image sensor and transferring it to a processor system.
  • A "memory" for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • A "signal generator" for generating a signal for the processor system in response to the quantity of data in the memory.
  • A "circuit" for controlling the transfer of data from the memory at a rate determined by the processor system.
• The complaint reserves the right to assert other claims, which may include dependent claims (Compl. ¶19).

Multi-Patent Capsule

• Patent Identification: U.S. Patent No. 8,537,242, "Host interface for imaging arrays," Issued September 17, 2013.
• Technology Synopsis: As a divisional of the ’790 patent, the ’242 patent addresses the same technical problem of interfacing an image sensor with a host processor. The invention is claimed as a method of processing imaging signals, which includes storing image data from a sensor in a FIFO memory, maintaining a count of the data in memory, and generating a request (such as an interrupt or bus request) to a processor to transfer the data once a predetermined amount has been accumulated (’242 Patent, Abstract).
• Asserted Claims: The complaint does not specify asserted claims, incorporating them by reference from an unprovided exhibit (Compl. ¶33). The patent's independent claims include method claims 1 and 8.
• Accused Features: The complaint alleges that the "Exemplary Defendant Products" infringe the ’242 patent but does not provide details outside of the unprovided claim charts (Compl. ¶¶ 28, 33).

III. The Accused Instrumentality

Product Identification

• The complaint identifies the accused instrumentalities as "Exemplary Defendant Products" within claim charts attached as Exhibits 4, 5, and 6 (Compl. ¶¶ 15, 24, 33).

Functionality and Market Context

• The complaint does not provide the referenced exhibits or any description of the accused products' names, models, or specific functionalities. Therefore, the complaint itself does not provide sufficient detail for an analysis of the accused instrumentality.

IV. Analysis of Infringement Allegations

The complaint’s infringement allegations for all asserted patents are made entirely by incorporating by reference the claim charts provided as Exhibits 4, 5, and 6 (Compl. ¶¶ 16, 25, 34). As these exhibits were not included with the complaint document, a detailed analysis of the specific infringement allegations is not possible. The complaint asserts that these charts demonstrate that the "Exemplary Defendant Products" satisfy all elements of the asserted claims (Compl. ¶¶ 15, 24, 33).

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

• Term: "memory means" (’527 Patent, Claim 1)

  • Context and Importance: This term is drafted in means-plus-function format under 35 U.S.C. § 112(f). Its scope will be limited to the corresponding structure described in the specification and its equivalents. The central dispute will be defining that structure and the range of its equivalents.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states that a related memory device in the prior art "can be a random access memory or any memory device," language that could be argued to apply more broadly (’527 Patent, col. 1:35-37).
    • Evidence for a Narrower Interpretation: The structure disclosed in the preferred embodiment that performs the function is "memory device 24," which is shown as a discrete component within the "interface module 21" (’527 Patent, Fig. 2; col. 2:50-51). An argument could be made that the scope is limited to this specific structural arrangement and its equivalents.

• Term: "a memory for storing imaging array data and clocking signals" (’790 Patent, Claim 1)

  • Context and Importance: Practitioners may focus on this term because the infringement analysis will depend on whether an accused device’s memory performs the dual function of storing both "data" and "clocking signals" and what it means to "store" clocking signals.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification states the memory "may be a first-in first-out (FIFO) buffer or an addressable memory," suggesting flexibility in the type of memory structure (’790 Patent, col. 2:12-14). One might argue "storing... clocking signals" refers to the memory system's use of clock signals for timing operations, not literal storage of the signal waveforms.
    • Evidence for a Narrower Interpretation: The claim language explicitly requires storing both data and signals. A defendant could argue this requires the physical storage of clocking signal values alongside pixel data, a function that a standard data buffer may not perform. The embodiment shows clock signals C_R and C_F bundled with data D_A on a bus "for storage in the buffer 44" (’790 Patent, Fig. 5; col. 5:11-14).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 patents. The factual basis for inducement is the allegation that Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents (Compl. ¶¶ 22, 31). Only direct infringement is alleged for the ’527 patent (Compl. ¶13; Prayer for Relief ¶B).
• Willful Infringement: The complaint does not use the term "willful." However, for the ’790 and ’242 patents, it alleges that service of the complaint itself constitutes "Actual Knowledge of Infringement" (Compl. ¶¶ 21, 30). This allegation provides a basis for potential post-suit enhancement of damages. No similar knowledge allegation is made for the ’527 patent.

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be evidentiary sufficiency: As the complaint's infringement theory is contained entirely within unprovided exhibits, a threshold question is whether the technical evidence, once produced, will be sufficient to show that the accused products practice every limitation of the asserted claims.
• A second core issue will be one of structural scope: For the ’527 patent, the case may turn on whether the accused products contain a "memory means" that is structurally equivalent to the patent's disclosed embodiment, which was specifically designed to replace the external buffer RAM found in the prior art.
• Finally, a key technical question for the ’790 and ’242 patents will concern system-level functionality: Does the accused interface operate as claimed by buffering data from an image sensor and generating a specific signal (e.g., an interrupt) to a host processor based on the quantity of data in the buffer, thereby managing an asynchronous transfer?