Cedar Lane Tech Inc v. Renesas Electronics Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Renesas Electronics Corporation (Japan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01031, W.D. Tex., 10/04/2022
• Venue Allegations: Venue is asserted as proper because the Defendant is a foreign corporation and has allegedly committed acts of patent infringement within the Western District of Texas.
• Core Dispute: Plaintiff alleges that Defendant’s electronics products infringe two patents related to an interface for transferring data from an imaging array to a host processor system.
• Technical Context: The technology concerns methods and systems for efficiently managing the data flow between a CMOS image sensor and a central processing unit, a foundational function in devices like digital cameras, smartphones, and automotive vision systems.
• Key Procedural History: The complaint states that Plaintiff is the assignee of the patents-in-suit. U.S. Patent No. 8,537,242 is a divisional of the application that resulted in U.S. Patent No. 6,972,790. No other significant procedural events are mentioned in the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,972,790 - “Host interface for imaging arrays” (issued Dec. 6, 2005)

The Invention Explained

• Problem Addressed: The patent’s background section describes a technological incompatibility between image sensors, which typically output a continuous "video style" data stream, and commercial microprocessors, which use an address-based data interface for random access. This mismatch requires "additional glue logic," which negates some of the cost and integration benefits of using CMOS technology for image sensors (ʼ790 Patent, col. 1:38-53).
• The Patented Solution: The invention proposes an interface, preferably integrated onto the same semiconductor die as the image sensor, to act as an intermediary. This interface uses a memory (such as a First-In-First-Out buffer) to temporarily store the image data as it arrives from the sensor. The interface then generates a signal, such as an interrupt, to alert the host processor when a certain amount of data has accumulated. A control circuit then manages the data transfer from the memory to the processor at a rate determined by the processor, effectively decoupling the sensor’s fixed timing from the processor’s variable-demand access ('790 Patent, Abstract; col. 2:4-14).
• Technical Importance: This architecture simplifies system design and reduces cost by enabling the tight integration of the sensor and its interface logic on a single CMOS die, a key advantage that CMOS imaging technology holds over older CCD technology ('790 Patent, col. 1:25-31).

Key Claims at a Glance

• The complaint asserts infringement of "exemplary claims" without specifying them (Compl. ¶12). Independent claim 1 is the broadest apparatus claim.
• Independent Claim 1 recites an interface comprising:
  • a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals;
  • a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory; and
  • a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system.

U.S. Patent No. 8,537,242 - “Host interface for imaging arrays” (issued Sep. 17, 2013)

The Invention Explained

• Problem Addressed: As a divisional of the '790 patent's application, this patent addresses the same problem of incompatibility between image sensor data streams and processor data interfaces ('242 Patent, col. 1:40-53).
• The Patented Solution: This patent claims a specific method for processing imaging signals. The method involves storing incoming image data in a FIFO memory, using a counter to track the amount of data in that memory, and comparing this count to a predefined limit. When the count reaches the limit, an interrupt signal is generated to request the processor to transfer the buffered data, thereby managing the data flow between the two components ('242 Patent, col. 8:56-68, Claim 1).
• Technical Importance: This method provides a concrete implementation of the system described in the '790 patent, detailing a logic-based process for managing the buffer and signaling the host processor.

Key Claims at a Glance

• The complaint asserts infringement of "exemplary claims" without specifying them (Compl. ¶21). Independent claim 1 is the broadest method claim.
• Independent Claim 1 recites a method comprising the steps of:
  • receiving image data from an imaging array;
  • storing the image data in a FIFO memory;
  • updating a FIFO counter to maintain a count of the image data;
  • comparing the count of the FIFO counter with a FIFO limit;
  • generating an interrupt signal to request a processor to transfer image data from the FIFO memory, based on the comparison and an enable signal; and
  • transferring the image data from the FIFO memory to the processor in response to the interrupt.

III. The Accused Instrumentality

Product Identification

The complaint refers generally to "Exemplary Defendant Products" (Compl. ¶12, ¶21).

Functionality and Market Context

The complaint alleges that these products are made, used, sold, and imported by Defendant Renesas Electronics Corporation (Compl. ¶12, ¶21). The complaint incorporates by reference Exhibits 3 and 4, which allegedly contain claim charts identifying the specific products and detailing their infringing functionality (Compl. ¶17-18, ¶26-27). However, these exhibits were not filed with the public version of the complaint. Therefore, the complaint does not provide sufficient detail for analysis of the specific accused products or their operation. No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint incorporates by reference claim charts from Exhibits 3 and 4, which were not available for this analysis. The infringement allegations are therefore summarized based on the complaint's narrative, and claim chart tables cannot be constructed.

• '790 Patent Infringement Allegations: The complaint alleges that the "Exemplary Defendant Products" directly infringe the '790 Patent by practicing the claimed technology (Compl. ¶12, ¶17). This suggests the products are alleged to contain an interface with a memory, a signal generator, and a control circuit that collectively manage data transfer from an image sensor to a processor in the manner claimed.
• '242 Patent Infringement Allegations: The complaint alleges that the "Exemplary Defendant Products" directly infringe the '242 Patent by practicing the claimed technology (Compl. ¶21, ¶26). This suggests the products are alleged to perform a method of using a FIFO memory, a counter, and a comparison to a limit to buffer image data and generate an interrupt for a processor.

Identified Points of Contention

• Technical Questions: A primary technical question will be one of architectural mapping. What evidence does the complaint provide that the accused Renesas products, which may be complex systems-on-a-chip (SoCs) with multiple general-purpose components, contain the specific, dedicated interface architecture recited by the claims? For the '242 Patent, a key question is whether the accused products perform the explicit method step of "updating a FIFO counter" and "comparing the count... with a FIFO limit", or if they use a functionally different buffer management scheme (e.g., based on read/write pointers).
• Scope Questions: For the '790 Patent, a key question of scope will be the interpretation of the broad term "circuit for controlling the transfer of the data". The dispute may focus on whether this term covers general-purpose hardware like a standard Direct Memory Access (DMA) controller, or if it is limited to a more specialized circuit as described in the patent's embodiments.

V. Key Claim Terms for Construction

Term 1 ('790 Patent, Claim 1): "a circuit for controlling the transfer of the data"

Context and Importance

This functional limitation is central to defining the scope of Claim 1. Its construction will determine whether a wide range of hardware implementations, from a simple state machine to a complex, programmable DMA controller, fall within the claim's boundaries.

Intrinsic Evidence for a Broader Interpretation

The claim language is functional and does not recite specific structure. The specification describes the circuit's purpose as controlling the data transfer "at a rate determined by the processor system" ('790 Patent, col. 2:11-14), which could support an interpretation covering any structure that achieves this result.

Intrinsic Evidence for a Narrower Interpretation

The patent discloses specific embodiments for this circuit, including a "Chip Command Decoder" (45), "FIFO Read Control" (47), and associated registers ('790 Patent, Fig. 2). A party could argue the term should be construed as limited to these disclosed structures and their equivalents.

Term 2 ('242 Patent, Claim 1): "updating a FIFO counter to maintain a count of the image data"

Context and Importance

This method step requires a specific mechanism for tracking the buffer's fill level. The infringement analysis will depend on whether the accused method uses a literal "counter" for this purpose or an alternative mechanism that a party might argue is different.

Intrinsic Evidence for a Broader Interpretation

A party might argue that "counter" should be interpreted functionally to mean any logical element that tracks the quantity of data, not necessarily a dedicated hardware counter that increments and decrements.

Intrinsic Evidence for a Narrower Interpretation

The term "counter" suggests a specific type of digital circuit. The specification's embodiment in Figure 5 explicitly depicts an "increment/decrement counter" (54) ('242 Patent, Fig. 5). This disclosure could support an argument that the claim requires this specific type of structure or its direct equivalent.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement, stating that Defendant distributes "product literature and website materials" that instruct end users on how to use the accused products in a manner that infringes the patents (Compl. ¶15, ¶24). The allegations state that Defendant has knowledge of its infringement at least since being served with the complaint (Compl. ¶16, ¶25).
• Willful Infringement: The willfulness claims are based on alleged post-suit knowledge. The complaint asserts that its service constitutes "actual knowledge of infringement" and that Defendant's continued infringing activities despite this knowledge are willful (Compl. ¶14-15, ¶23-24).

VII. Analyst’s Conclusion: Key Questions for the Case

1. Architectural Mapping: A core issue will be whether the functional architecture of the accused Renesas products maps onto the specific elements recited in the patent claims. The case will likely require a detailed technical comparison to determine if the products contain the claimed "memory", "signal generator", and "control circuit" of the '790 patent, and if they perform the specific "counter" and "comparison" steps of the '242 patent's method claims, or if they achieve a similar result using a fundamentally different, more general-purpose architecture.
2. Definitional Scope: The dispute may turn on the construction of key claim terms. Can the broad, functional term "circuit for controlling the transfer" in the '790 patent be interpreted to cover a standard, multi-purpose DMA controller found in modern SoCs, or is it limited to a more specialized interface? This question of scope will be critical in determining the reach of the patents over modern integrated circuit designs.