Cedar Lane Tech Inc v. Socionext Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Socionext Inc. (Japan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01061, W.D. Tex., 10/07/2022
• Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation, and Plaintiff alleges that Defendant has committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that certain of Defendant's products infringe two patents related to an interface for transferring data from an image sensor to a processor system.
• Technical Context: The technology addresses methods and systems for efficiently buffering image data from a sensor before transferring it to a host processor, a common architecture in digital imaging devices.
• Key Procedural History: U.S. Patent No. 8,537,242 is a divisional of the application that resulted in U.S. Patent No. 6,972,790, indicating a close technical and prosecution relationship between the two patents-in-suit.

Case Timeline

Date	Event
2000-01-21	Priority Date for ’790 and ’242 Patents
2005-12-06	U.S. Patent No. 6,972,790 Issued
2013-09-17	U.S. Patent No. 8,537,242 Issued
2022-10-07	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays" (Issued Dec. 6, 2005)

The Invention Explained

• Problem Addressed: The patent’s background explains that the continuous "video style" data output from CMOS image sensors is incompatible with the data interface of commercial microprocessors, which are designed for random data access. This mismatch necessitates "additional glue logic," which undermines the cost-effectiveness of using CMOS technology (ʼ790 Patent, col. 1:47-53).
• The Patented Solution: The invention proposes an interface, preferably integrated onto the same semiconductor die as the image sensor, that bridges this gap. The interface uses a memory, such as a First-In-First-Out (FIFO) buffer, to temporarily store data arriving from the sensor. Once a certain amount of data accumulates in the memory, the interface generates a signal (e.g., an interrupt) to alert the host processor. The interface then manages the transfer of the buffered data to the processor at a rate controlled by the processor, not the sensor, thereby decoupling the two components (ʼ790 Patent, Abstract; col. 2:3-14).
• Technical Importance: This architecture allows the main processor to perform other tasks without being tied to the image sensor's constant data stream, improving system efficiency and reducing the need for complex external circuitry (ʼ790 Patent, col. 3:25-29).

Key Claims at a Glance

• The complaint asserts "exemplary claims" incorporated by reference in an external exhibit (Compl. ¶12). Independent claim 1 is representative of the invention's core apparatus.
• Independent Claim 1 requires:
  • An interface for receiving data from an image sensor.
  • A memory for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • A signal generator that generates a signal for the processor system in response to the quantity of data in the memory.
  • A circuit for controlling the data transfer from the memory at a rate determined by the processor system.

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays" (Issued Sep. 17, 2013)

The Invention Explained

• Problem Addressed: Like its parent, the ’242 Patent addresses the incompatibility between the fixed-rate output of an image sensor and the asynchronous, command-based nature of a host processor (ʼ242 Patent, col. 1:42-53).
• The Patented Solution: The ’242 Patent claims the method of operating such an interface. It describes the steps of receiving and storing image data in a FIFO memory, maintaining a count of the data in that memory, comparing the count to a predefined limit, and, based on that comparison, generating an interrupt to request the processor to initiate a data transfer (’242 Patent, Claim 1).
• Technical Importance: By claiming the method of use, this patent provides a different layer of protection that complements the apparatus claims of the parent ’790 Patent, covering the dynamic process of managing data flow between the sensor and processor.

Key Claims at a Glance

• The complaint asserts "exemplary claims" incorporated by reference in an external exhibit (Compl. ¶21). Independent claim 1 is representative of the core method.
• Independent Claim 1 requires the steps of:
  • Receiving image data from an imaging array.
  • Storing the image data in a FIFO memory.
  • Updating a FIFO counter to maintain a count of the image data.
  • Comparing the counter's count with a FIFO limit.
  • Generating an interrupt signal to a processor based on the comparison and an enable signal.
  • Transferring image data from the FIFO memory to the processor in response to the interrupt.

III. The Accused Instrumentality

Product Identification

The complaint identifies infringing products as the "Exemplary Defendant Products" but refers to external Exhibits 3 and 4 for their specific identification (Compl. ¶¶ 12, 21). These exhibits were not provided for analysis.

Functionality and Market Context

The complaint does not provide any description of the accused products' technical functionality, operation, or market context, other than to state that they practice the claimed technology as detailed in the non-public exhibits (Compl. ¶¶ 17, 26).

IV. Analysis of Infringement Allegations

The complaint incorporates infringement allegations by reference to external claim chart exhibits (Exhibits 3 and 4), which were not provided for this analysis. Therefore, a detailed claim chart summary cannot be constructed. No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • ’790 Patent (Apparatus): A primary issue will be whether the accused products contain the claimed hardware structures. A technical question will be what evidence shows that the accused products include a "signal generator" that operates "in response to the quantity of data in the memory" as claimed, rather than a more generic signaling mechanism. Further, the analysis will focus on whether the data transfer from the buffer is controlled "at a rate determined by the processor system," which requires showing the processor, not the sensor, dictates the transfer speed.
  • ’242 Patent (Method): The dispute will likely focus on whether the accused products, when operating, perform the specific sequence of logical steps recited in the claims. A key evidentiary question will be whether Plaintiff can demonstrate that the accused devices internally perform the steps of "updating a FIFO counter," "comparing the count...with a FIFO limit," and generating an interrupt specifically "in response to" that comparison.

V. Key Claim Terms for Construction

• The Term: "a memory for storing imaging array data and clocking signals" (’790 Patent, Claim 1)
  • Context and Importance: The construction of this term is critical to defining the scope of the claimed memory. Practitioners may focus on this term because its interpretation determines whether the patent requires a single memory structure that holds both pixel information and timing signals, or if it covers systems where clock signals are merely used to time the storage of pixel data.
  • Intrinsic Evidence for a Broader Interpretation: The specification discloses an embodiment where "output Da, row clock CR and frame clock CF are bundled onto a single bus 51 for storage in the buffer 44," which could support an interpretation that storing the effects or sequence of clock signals alongside data meets the limitation (’790 Patent, col. 5:11-14).
  • Intrinsic Evidence for a Narrower Interpretation: A defendant may argue that the plain language "storing... clocking signals" requires the physical storage of bits representing the clock signals themselves, not just using those signals to time the storage of other data.
• The Term: "predetermined relationship to the FIFO limit" (’242 Patent, Claim 1)
  • Context and Importance: This term defines the trigger condition for generating the interrupt signal. Its construction will be central to determining what types of buffer management logic fall within the claim's scope.
  • Intrinsic Evidence for a Broader Interpretation: Plaintiff may argue that the phrase "predetermined relationship" is intentionally broad and covers any pre-set logical condition, such as "greater than," "equal to," or "not empty." The specification provides an example of "Sc≥SL," which is one such relationship but not necessarily the only one (’790 Patent, col. 6:11-12, intrinsic evidence from parent patent).
  • Intrinsic Evidence for a Narrower Interpretation: A defendant could argue that the example embodiment (Sc≥SL) limits the term's meaning to a high-water-mark threshold comparison. This could be used to argue that other triggering mechanisms, such as signaling whenever any data is present, do not have the required "relationship to the FIFO limit."

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for both patents. The basis for inducement is the allegation that Defendant distributes "product literature and website materials" that instruct customers and end users to operate the accused products in a manner that directly infringes the patent claims (Compl. ¶¶ 15, 24). Knowledge is alleged to exist at least from the date the complaint was served (Compl. ¶¶ 16, 25).
• Willful Infringement: The complaint does not use the term "willful." However, it asserts that the service of the complaint and its attached claim charts provides Defendant with "Actual Knowledge of Infringement" and that Defendant continues to infringe despite this knowledge (Compl. ¶¶ 14-15, 23-24). These allegations could form the basis for a later claim of post-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

1. An Evidentiary Question of Proof: As the complaint’s infringement contentions are contained entirely within non-public exhibits and the accused products are not specifically identified, a threshold question is what evidence Plaintiff can marshal to show that Defendant’s products contain the specific memory, counter, and signaling architecture recited in the asserted claims.
2. A Dispute Over Operational Logic: For the ’242 method patent, the case will likely involve a dispute over operational correspondence. The key question is whether the accused products’ data management systems execute the specific claimed sequence—notably, comparing a data count to a limit to trigger an interrupt—or if they achieve a similar result through a fundamentally different technical process.
3. A Definitional Question of Claim Scope: The outcome may depend on how the court construes the phrase "storing... clocking signals" in the ’790 patent. The case may turn on whether this is interpreted to require the literal storage of clock signal data in memory or can be read more broadly to cover a memory system that is merely timed by such signals.