Cedar Lane Tech Inc v. Wonwoo Engineering Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Wonwoo Engineering Co., Ltd. (South Korea)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01072, W.D. Tex., 10/11/2022
• Venue Allegations: Venue is alleged to be proper on the basis that the defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant’s imaging and camera products infringe three U.S. patents related to interfacing image sensors with data compression and processing systems.
• Technical Context: The technology concerns methods for efficiently transferring image data from a sensor to a processing or compression chip, a foundational process in digital cameras, scanners, and surveillance systems.
• Key Procedural History: The complaint identifies Plaintiff as the assignee of the patents-in-suit. U.S. Patent No. 8,537,242 is a divisional of the application that issued as U.S. Patent No. 6,972,790, and they share a common specification. No other significant procedural events are mentioned in the complaint.

Case Timeline

Date	Event
1999-06-01	’527 Patent Priority Date
2000-01-21	’790 and ’242 Patents Priority Date
2002-10-29	’527 Patent Issue Date
2005-12-06	’790 Patent Issue Date
2013-09-17	’242 Patent Issue Date
2022-10-11	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued Oct. 29, 2002

The Invention Explained

• Problem Addressed: The patent describes that conventional systems for JPEG image compression required an extra, external memory chip (typically RAM) to act as a buffer between the analog-to-digital (A/D) converter and the JPEG compression integrated circuit (’527 Patent, col. 1:43-52). This was necessary because the compression algorithm processes data in fixed-size blocks (e.g., 8x8 pixels), while the A/D converter outputs data line-by-line, creating a mismatch that the external memory had to resolve (’527 Patent, col. 1:33-49).
• The Patented Solution: The invention proposes an interface module that eliminates the need for this separate, external memory buffer (’527 Patent, col. 1:53-57). The module contains its own memory, which is sized to store a specific number of image lines (e.g., eight lines) corresponding to the height of a compression block (’527 Patent, col. 3:4-9). After filling its internal memory, the module's control logic reads out the data in correctly sized blocks (e.g., 8x8 pixels) and sends them directly to the JPEG compression device, as illustrated in Figure 2 of the patent (’527 Patent, col. 2:3-21; Fig. 2).
• Technical Importance: This design sought to reduce the component count, cost, and complexity of digital imaging hardware by integrating the necessary buffering function into an interface module and removing a discrete memory chip from the system architecture (’527 Patent, col. 2:22-24).

Key Claims at a Glance

• The complaint incorporates by reference an exhibit listing the asserted claims, which was not filed with the complaint (Compl. ¶15). Analysis of independent claim 1 is representative:
• Claim 1 recites a module comprising:
  • "read control means" for reading a predetermined number of image lines from an A/D converter and generating a control signal.
  • "memory means" for storing the image lines, where the memory is capable of storing the same number of lines as the JPEG compression device's built-in memory.
  • "output control means" that responds to the control signal to read an image block from the memory and forward it to the JPEG device's built-in memory.
• The complaint does not explicitly reserve the right to assert dependent claims but refers generally to infringement of "one or more claims" (Compl. ¶13).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued Dec. 6, 2005

The Invention Explained

• Problem Addressed: The patent explains that standard CMOS image sensors produce a "video style output"—a continuous, synchronized stream of pixel data—which is fundamentally incompatible with the architecture of commercial microprocessors (’790 Patent, col. 1:38-46). Processors are designed to access data from a memory space using address signals, not to passively receive a high-speed data stream. Bridging this gap required "additional glue logic," which increased system cost and complexity (’790 Patent, col. 1:47-53).
• The Patented Solution: The patent describes an interface, preferably integrated onto the same semiconductor die as the image sensor, that serves as an intelligent bridge (’790 Patent, col. 2:25-34). This interface includes a memory (such as a FIFO buffer) to store the incoming pixel data from the sensor array (’790 Patent, Abstract). A signal generator monitors the amount of data in the buffer and, upon reaching a certain level, generates a signal (e.g., an interrupt) to alert the main processor that data is ready for transfer (’790 Patent, col. 2:8-11). A control circuit then manages the transfer of this buffered data to the system bus at a rate determined by the processor, not the sensor (’790 Patent, col. 2:11-14).
• Technical Importance: This integrated interface allows a standard microprocessor to efficiently acquire data from a CMOS image sensor without requiring extensive external buffering and control circuitry, thereby realizing the full cost-saving potential of CMOS imaging technology (’790 Patent, col. 1:63-66).

Key Claims at a Glance

• The complaint incorporates by reference an exhibit listing the asserted claims, which was not filed with the complaint (Compl. ¶24). Analysis of independent claim 1 is representative:
• Claim 1 recites an interface comprising:
  • a "memory" for storing imaging array data and clocking signals at a rate determined by those signals.
  • a "signal generator" for generating a signal for the processor system "in response to the quantity of data in the memory".
  • a "circuit for controlling the transfer" of data from the memory at a rate determined by the processor system.
• The complaint does not explicitly reserve the right to assert dependent claims but refers generally to infringement of "one or more claims" (Compl. ¶19).

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued Sep. 17, 2013

• Technology Synopsis: This patent shares its specification with the ’790 Patent and addresses the same technical problem of bridging the architectural gap between a CMOS image sensor's continuous data stream and a microprocessor's memory-mapped access methods (’242 Patent, col. 1:10-12). The invention is an integrated circuit containing both the imaging array and an on-die interface; this interface uses a buffer to store image data and control circuitry to alert the system processor and manage the subsequent data transfer to the system bus (’242 Patent, col. 2:25-40).
• Asserted Claims: The complaint alleges infringement of "Exemplary ’242 Patent Claims" identified in the incorporated Exhibit 6, which was not filed with the complaint (Compl. ¶¶ 28, 33).
• Accused Features: The complaint alleges that the "Exemplary Defendant Products" practice the technology claimed in the ’242 Patent, but does not specify which features of those products are accused beyond incorporating the (unavailable) claim charts by reference (Compl. ¶33).

III. The Accused Instrumentality

• Product Identification: The complaint refers to "Exemplary Defendant Products" that are identified in claim chart exhibits incorporated by reference (Compl. ¶¶ 13, 19, 28). As these exhibits were not filed with the complaint, the specific accused products are not identified in the pleading itself.
• Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the accused products' functionality. It alleges in a conclusory manner that the products "practice the technology claimed" by the patents-in-suit and that the products' components "satisfy all elements" of the asserted claims (Compl. ¶¶ 15, 24, 33). No specific allegations regarding the products' market position or commercial importance are made.

IV. Analysis of Infringement Allegations

The complaint incorporates infringement allegations by reference to claim chart exhibits (Exhibits 4, 5, and 6), which were not provided with the filed pleading (Compl. ¶¶ 16, 25, 34). Therefore, a detailed element-by-element analysis is not possible. The narrative theory of infringement for each patent is that unspecified "Exemplary Defendant Products" contain the necessary hardware and/or software to practice each element of certain "Exemplary" claims (Compl. ¶¶ 15, 24, 33).

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • For the ’527 Patent: A likely point of contention will be whether the architecture of the accused products maps onto the distinct functional modules required by the claims. The analysis may raise the question of whether a modern, highly integrated system-on-a-chip (SoC) in an accused product contains separate "read control means", "memory means", and "output control means", or if these functions are performed by a single, multi-purpose processing unit in a manner that is inconsistent with the claimed structure.
  • For the ’790 and ’242 Patents: A central technical question will concern the trigger mechanism for data transfer. The infringement analysis will likely focus on whether the accused products' interface alerts the processor "in response to the quantity of data in the memory," as claimed. A dispute may arise if the accused products use a different mechanism, such as a fixed-time interval or a processor-initiated polling schedule, rather than a buffer-fullness trigger.

V. Key Claim Terms for Construction

• From the ’527 Patent:

  • The Term: "memory means ... capable of storing the same number of image lines as said built-in memory device" (from Claim 1).
  • Context and Importance: This term is critical as it defines the specific relationship between the invention's intermediate memory and the JPEG compressor's own internal buffer. The infringement analysis may turn on whether the accused product's memory architecture meets this "same number of image lines" requirement.
  • Intrinsic Evidence for a Broader Interpretation: The claim uses the word "capable," which may support an interpretation that the device must only have the ability to be configured this way, not that it must operate this way at all times (’527 Patent, col. 4:5-7).
  • Intrinsic Evidence for a Narrower Interpretation: The specification repeatedly emphasizes this size-matching as a key aspect of the solution, stating, for example, that if the compression unit is 8x8 pixels, "the memory device 24 can save 8 lines of image data" (’527 Patent, col. 3:7-9). This may support an argument that the specific size correspondence is a limiting feature of the invention.

• From the ’790 Patent:

  • The Term: "a signal generator for generating a signal ... in response to the quantity of data in the memory" (from Claim 1).
  • Context and Importance: This term defines the core logic for initiating data transfer from the interface to the processor. The case may hinge on how the accused products determine when to send this signal. Practitioners may focus on this term because it requires a causal link between the amount of data stored and the generation of the signal.
  • Intrinsic Evidence for a Broader Interpretation: The claim language is general and does not require a specific threshold. The specification describes the signal being generated when the interface has "an amount of data approaching the limits of its storage capacity," which could encompass a range of quantitative triggers (’790 Patent, col. 6:28-30).
  • Intrinsic Evidence for a Narrower Interpretation: The detailed description discloses a specific implementation where an "interrupt generator 48 compares the FIFO counter output Sc and the FIFO limit SL," and asserts the signal if "Sc ≥ SL" (’790 Patent, col. 6:11-14). This could be used to argue that the term requires a direct comparison to a pre-set quantitative limit.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 patents. The allegations are based on Defendant selling the accused products and distributing "product literature and website materials" that allegedly instruct customers on how to use the products in an infringing manner (Compl. ¶¶ 22-23, 31-32).
• Willful Infringement: Willfulness is alleged for the ’790 and ’242 patents. The allegations are based entirely on post-suit conduct. The complaint asserts that service of the complaint and its attached (but un-filed) claim charts provides Defendant with "actual knowledge of infringement," and that any continued infringement thereafter is willful (Compl. ¶¶ 21-22, 30-31).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of structural correspondence: for the ’527 patent, can the distinct "read control means", "memory means", and "output control means" recited in the claims be mapped onto the components of a modern, integrated chipset, or does the accused architecture merge these functions in a way that falls outside the claim scope?
2. A key technical question for the ’790 and ’242 patents will be one of operational mechanism: does the accused interface initiate data transfer based on a trigger that is truly "in response to the quantity of data in the memory" as the claims require, or is it governed by a different logic, such as fixed timing or direct processor polling, that may not meet this limitation?
3. An initial evidentiary question will be one of pleading sufficiency: given that the complaint's specific infringement allegations are made solely by incorporating external exhibits that were not filed, the parties may dispute whether the complaint provides sufficient notice of the infringement theories under federal pleading standards.