Cedar Lane Tech Inc v. Konica Minolta Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Konica Minolta, Inc. (Japan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01074, W.D. Tex., 10/12/2022
• Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation, which may be sued in any judicial district.
• Core Dispute: Plaintiff alleges that Defendant infringes three patents related to interface modules and methods for efficiently managing the flow of image data between an image sensor, a memory buffer, and a processor.
• Technical Context: The patents address methods for handling high-speed data from image sensors (like those in digital cameras or scanners) and preparing it for processing or compression, a foundational challenge in digital imaging system design.
• Key Procedural History: The '790 and '242 patents are part of the same patent family; U.S. Patent 8,537,242 is a divisional of the application that led to U.S. Patent 6,972,790, which itself claims priority to a 2000 provisional application. This shared specification may allow arguments made during the prosecution of one patent to be applied to the other under the doctrine of prosecution history estoppel.

Case Timeline

Date	Event
1999-06-01	'527 Patent Application Filed
2000-01-21	'790 & '242 Patents Priority Date (Provisional Filed)
2000-12-21	'790 Patent Application Filed
2002-10-29	'527 Patent Issued
2005-10-27	'242 Patent Application Filed
2005-12-06	'790 Patent Issued
2013-09-17	'242 Patent Issued
2022-10-12	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002 (’527 Patent)

The Invention Explained

• Problem Addressed: The patent describes a problem in conventional digital imaging systems where image data must be passed from an analog-to-digital (A/D) converter to a JPEG compression chip. Because the compression chip processes data in fixed-size units (e.g., 8x8 pixel blocks), an "extra memory device," typically a large RAM, is required to buffer the incoming image data before it can be formatted into these blocks, adding cost and inefficiency ('527 Patent, col. 1:33-57).
• The Patented Solution: The invention proposes an "interface module" that sits between the A/D converter and the JPEG compression device. This module contains a smaller, purpose-built memory device designed to store just enough lines of image data (e.g., 8 lines) to form one compression block. The module's read controller fills this small memory line-by-line, and once full, its output controller sends a properly sized "image block" directly to the JPEG device's internal memory. This eliminates the need for the large, external RAM buffer previously used for this task ('527 Patent, Abstract; col. 2:48-63; Fig. 2).
• Technical Importance: This approach provided a method to reduce the component cost and complexity of digital imaging hardware by optimizing memory management to suit the specific requirements of the JPEG compression standard.

Key Claims at a Glance

• The complaint does not specify which claims of the ’527 Patent are asserted, instead referring to "Exemplary '527 Patent Claims" identified in an un-provided exhibit (Compl. ¶¶13, 15). The patent’s independent claims are 1 (an apparatus) and 8 (a method).
• Independent Claim 1 (Module):
  • read control means for sequentially reading a predetermined number of image lines from an analog/digital converter;
  • memory means for storing said image lines, which is "capable of storing the same number of image lines as said built-in memory device" of a JPEG compression means; and
  • output control means for sequentially reading an "image block" from the memory means and forwarding it to the built-in memory device.
• Independent Claim 8 (Method):
  • sequentially reading a predetermined number of image lines;
  • storing the lines in a memory means "capable of storing the same number of image lines as said built-in memory device"; and
  • sequentially reading a predetermined size of "image block" from the memory means to the built-in memory device when compression is required.

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005 (’790 Patent)

The Invention Explained

• Problem Addressed: The patent notes that the continuous "video style output" from a CMOS image sensor is often incompatible with the data interface of a commercial microprocessor, which expects to access data from specific memory addresses. This mismatch necessitates "additional glue logic" to bridge the two, undermining the cost-effectiveness of integrating the sensor and processing logic onto a single chip ('790 Patent, col. 1:46-60).
• The Patented Solution: The invention describes an interface, preferably integrated onto the same semiconductor die as the image sensor, that acts as an intelligent buffer. It uses a memory (such as a FIFO buffer) to receive and store data from the imaging array at the sensor's clock rate. A "signal generator" monitors the amount of data in the memory and, upon reaching a certain quantity, sends a signal (e.g., an interrupt) to the host processor. This alerts the processor to read the buffered data at its own pace, effectively decoupling the timing of the sensor and the processor ('790 Patent, Abstract; col. 2:4-13).
• Technical Importance: This invention facilitates the creation of more highly integrated and cost-effective "system-on-a-chip" designs for digital cameras by solving a fundamental data-rate mismatch problem between the image sensor and the main processor.

Key Claims at a Glance

• The complaint does not specify which claims of the ’790 Patent are asserted, instead referring to "Exemplary '790 Patent Claims" identified in an un-provided exhibit (Compl. ¶¶19, 24). The patent’s independent claims are 1, 8, and 15.
• Independent Claim 1 (Interface):
  • a memory for storing imaging array data at a rate determined by clocking signals;
  • a signal generator for generating a signal for the processor system "in response to the quantity of data in the memory"; and
  • a circuit for controlling the transfer of data from the memory at a rate determined by the processor system.
• Independent Claim 8: An interface similar to claim 1, but wherein the memory is an "addressable memory."
• Independent Claim 15 (Integrated Circuit):
  • an imaging array sensor integrated on a die; and
  • an interface integrated on the same die, which includes a memory for storing image data and a circuit for controlling its transfer to a data bus.

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued September 17, 2013 (’242 Patent)

• Technology Synopsis: As a divisional of the '790 Patent's application, the ’242 Patent addresses the same technical problem of interfacing an image sensor with a processor system. The disclosed solution similarly involves an interface with a memory buffer to decouple the differing data rates. This patent further details a control scheme where the interface can generate a "bus request signal" to gain control of a system bus to transfer the stored image data, a common alternative to the interrupt-based method.
• Asserted Claims: The complaint does not specify which claims are asserted, referring to "Exemplary '242 Patent Claims" in an un-provided exhibit (Compl. ¶¶28, 33). The patent’s independent claims are 1, 8, and 14.
• Accused Features: The complaint accuses unspecified "Exemplary Defendant Products" of infringement (Compl. ¶28). The specific features are allegedly detailed in Exhibit 6, which was not provided with the complaint (Compl. ¶33).

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products, methods, or services by name. It refers generally to "Exemplary Defendant Products" (Compl. ¶13).

Functionality and Market Context

• The complaint does not provide sufficient detail for analysis of the accused instrumentality's functionality, features, or market position. It alleges that infringement details are contained in Exhibits 4, 5, and 6, which are incorporated by reference but were not provided with the complaint (Compl. ¶¶15, 24, 33).

IV. Analysis of Infringement Allegations

The complaint alleges infringement of the patents-in-suit but relies on external exhibits to provide the specific claim charts mapping patent limitations to features of the accused products. As these exhibits (Exhibits 4, 5, and 6) were not provided with the complaint, the infringement allegations are summarized below in prose.

• ’527 Patent Infringement Allegations: Plaintiff alleges that Defendant’s "Exemplary Defendant Products" directly infringe one or more claims of the ’527 Patent by making, using, selling, or importing them in the U.S. (Compl. ¶13). The complaint states that Exhibit 4 contains charts demonstrating that these products "practice the technology claimed by the '527 Patent" and satisfy all elements of the asserted claims (Compl. ¶15).
• ’790 Patent Infringement Allegations: Plaintiff alleges that Defendant directly infringes one or more claims of the ’790 Patent (Compl. ¶19). The complaint states that Exhibit 5 contains charts demonstrating that the "Exemplary Defendant Products" practice the claimed technology and satisfy all elements of the asserted claims (Compl. ¶24).

Identified Points of Contention

• Evidentiary Questions: A threshold issue for the entire case is the lack of specificity in the complaint. A central question will be whether Plaintiff can produce evidence linking its general infringement allegations to specific, named Konica Minolta products and their technical operation.
• Scope and Technical Questions (’527 Patent): The infringement analysis may focus on whether an accused device’s memory architecture meets the specific structural limitations of the claims. Key questions may include: Does the accused device contain a memory that is "capable of storing the same number of image lines" as a separate, downstream JPEG compression device? Does it output data in an "image block" format as defined by the patent? A mismatch in this specific memory sizing and data formatting could suggest non-infringement.
• Scope and Technical Questions (’790 Patent): For the ’790 Patent, a dispute may arise over the claimed control mechanism. A key question is whether the accused interface generates an alert signal "in response to the quantity of data in the memory," as required by claim 1. The analysis will likely examine if the accused system uses a threshold-based trigger as described in the patent, or if it employs a different data control logic that is not based on the buffer's fill level.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

For the ’527 Patent

• The Term: "image block" (Claim 1)
• Context and Importance: The definition of this term is critical for determining whether the data format output by the accused interface module infringes. The dispute will likely center on whether the term is limited to the specific 8x8 pixel block used in JPEG compression or if it can cover other data structures.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Narrower Interpretation: The specification repeatedly links the invention to the JPEG standard, stating "the basic compression unit is an image block of 8x8 pixels" ('527 Patent, col. 1:39-42). This suggests the term is meant to be construed specifically as the unit required by a JPEG compressor.
  • Evidence for a Broader Interpretation: The term itself is generic. A party might argue that in the absence of an explicit definition limiting "image block" to 8x8 pixels, it should be given its plain and ordinary meaning of any discrete block of image data.

For the ’790 Patent

• The Term: "a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory" (Claim 1)
• Context and Importance: This limitation defines the core trigger mechanism of the patented interface. The case may turn on how closely the accused device's control logic must track the "quantity of data" to infringe. Practitioners may focus on this term because it appears to require a specific causal link between the amount of data in the buffer and the generation of the alert signal.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Narrower Interpretation: The specification describes a specific embodiment where an "increment/decrement counter" (54) tracks writes and reads, and its output (Sc) is compared to a pre-set "FIFO limit" (SL) to trigger an interrupt ('790 Patent, col. 6:11-15; Fig. 2). This supports a construction requiring a quantitative, threshold-based trigger.
  • Evidence for a Broader Interpretation: The claim language is broader than the specific embodiment. A party could argue that any system where the signal is generated as a logical consequence of data being present in the memory (e.g., after a full line of data is written) meets the "in response to the quantity" limitation, even without a specific counter or threshold comparison.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 patents. The factual basis alleged is that Defendant distributes "product literature and website materials" that instruct and encourage end users to operate the accused products in a manner that infringes the patents (Compl. ¶¶22, 31).
• Willful Infringement: The complaint alleges that Defendant gained "actual knowledge" of the ’790 and ’242 patents upon service of the complaint and the attached claim charts (Compl. ¶¶21, 30). It is alleged that any continued infringing activity after this date constitutes willful infringement, potentially justifying enhanced damages and a finding that the case is "exceptional" under 35 U.S.C. § 285 (Compl. ¶¶22, 31, J.i).

VII. Analyst’s Conclusion: Key Questions for the Case

This litigation appears to be in its earliest stages, with the complaint providing a high-level outline of the dispute. The resolution of the case will likely depend on the answers to several key questions:

1. An Evidentiary Question of Specificity: Can the Plaintiff successfully connect its broad allegations to specific Konica Minolta products? The complaint's failure to name any accused product suggests that a primary battleground will be discovery and the identification of the accused instrumentalities.
2. A Question of Structural Equivalence: For the '527 patent, a core issue will be whether the accused products contain a memory architecture that is structurally and functionally equivalent to the claimed "interface module." The analysis will likely focus on whether any buffer used in the accused systems is specifically sized and controlled to match a downstream compression unit, as the claim language appears to require.
3. A Question of Functional Operation: For the '790 and '242 patents, the central dispute will likely be the nature of the control logic. The key question is whether the accused interfaces operate by generating a processor alert "in response to the quantity of data in the memory," or if they rely on an alternative timing or data-flow control mechanism that falls outside the scope of the claims.