Cedar Lane Tech Inc v. SZ DJI Technology Co Ltd

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: SZ DJI Technology Co., Ltd. (China)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01079, W.D. Tex., 10/13/2022
• Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant’s drone and digital imaging products infringe three patents related to methods for efficiently interfacing image sensors with compression hardware and host processors.
• Technical Context: The patents address foundational challenges in digital imaging systems, specifically managing the flow of data from a sensor to processing and storage components, a core function in devices like digital cameras and drones.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit. U.S. Patent No. 8,537,242 is a divisional of the application that matured into U.S. Patent No. 6,972,790, indicating a shared specification and priority date between the two.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002.

The Invention Explained

• Problem Addressed: The patent’s background section describes an inefficiency in conventional digital imaging systems where an "extra memory device," typically RAM, is required to buffer image data between an analog-to-digital (A/D) converter and a JPEG compression integrated circuit (’527 Patent, col. 1:26-40). This is necessary because the JPEG algorithm processes data in fixed-size blocks (e.g., 8x8 pixels), while the A/D converter provides a continuous stream of data, creating a mismatch that the extra memory must resolve (’527 Patent, col. 1:41-52).
• The Patented Solution: The invention proposes an interface "module" containing a memory device specifically sized to match the internal memory of the JPEG compression device (’527 Patent, Abstract). This module reads a predetermined number of image lines (e.g., eight lines) from the A/D converter, stores them, and then forwards correctly sized image blocks (e.g., 8x8 pixels) to the JPEG device, thereby eliminating the need for the separate, external RAM buffer (’527 Patent, col. 3:1-18).
• Technical Importance: This design aims to reduce the hardware cost, footprint, and complexity of imaging devices like scanners or digital cameras by creating a more efficient data pipeline tailored to the requirements of the JPEG compression standard (’527 Patent, col. 1:52-55).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, instead referring to the "Exemplary '527 Patent Claims" identified in an external chart (Compl. ¶13). Assuming the assertion of the primary independent claim, Claim 1 recites:
  • A module for interfacing an A/D converter and a JPEG compression device with a built-in memory.
  • The module comprises a "read control means" for reading a predetermined number of image lines.
  • It includes a "memory means" "capable of storing the same number of image lines as said built-in memory device."
  • It also includes an "output control means" for "sequentially reading an image block" from the memory means and forwarding it to the JPEG device.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005.

The Invention Explained

• Problem Addressed: The patent describes a fundamental incompatibility between the "video style output" of CMOS image sensors, which provide a continuous, clock-synchronized data stream, and the interface of commercial microprocessors, which access memory randomly using address and control signals (’790 Patent, col. 1:37-52). Bridging this gap conventionally requires "additional glue logic" and memory, which negates the cost advantages of creating an integrated sensor-processor system on a single chip (’790 Patent, col. 1:56-63).
• The Patented Solution: The patent discloses an interface, preferably integrated on the same die as the image sensor, that decouples the two components (’790 Patent, col. 2:25-34). The interface uses an internal memory, such as a First-In First-Out (FIFO) buffer, to store the incoming pixel data from the sensor. When the amount of data in this memory reaches a certain point, a signal generator alerts the host processor (e.g., via an interrupt), which can then read the buffered data at its own speed, independent of the sensor's clock rate (’790 Patent, Abstract).
• Technical Importance: By providing an efficient, integrated bridge between the sensor and processor, the invention facilitates the development of more compact and cost-effective "system on a chip" (SoC) imaging solutions (’790 Patent, col. 1:26-30).

Key Claims at a Glance

• The complaint does not identify specific asserted claims, referring to the "Exemplary '790 Patent Claims" in an external chart (Compl. ¶19). Assuming the assertion of the primary independent claim, Claim 1 recites:
  • An interface for receiving data from an image sensor and transferring it to a processor system.
  • The interface comprises a "memory" for storing the image data.
  • It includes "a signal generator for generating a signal" for the processor "in response to the quantity of data in the memory".
  • It also includes "a circuit for controlling the transfer of the data" from the memory at a rate determined by the processor.
• The complaint does not explicitly reserve the right to assert dependent claims.

Multi-Patent Capsule: U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued September 17, 2013.

• Technology Synopsis: As a divisional of the application that led to the ’790 Patent, the ’242 Patent addresses the same technical problem of interfacing an image sensor with a processor system (’242 Patent, col. 1:10-14). The claimed invention is a method of processing imaging signals that involves receiving and storing image data in a FIFO memory, using a counter to track the amount of data in the memory, and generating a transfer request (like an interrupt or bus request) when the data count reaches a predetermined limit (’242 Patent, Abstract; Claim 1).
• Asserted Claims: The complaint does not specify which claims are asserted, referencing "Exemplary '242 Patent Claims" in an external exhibit (Compl. ¶28).
• Accused Features: The complaint alleges infringement by "Exemplary Defendant Products" but refers to an external exhibit for the identification of these products and the specific features alleged to infringe (Compl. ¶¶ 28, 33).

III. The Accused Instrumentality

The complaint identifies the accused instrumentalities as the "Exemplary Defendant Products" and states that they are detailed in Exhibits 4, 5, and 6, which are incorporated by reference (Compl. ¶¶ 15, 24, 33). These exhibits were not attached to the publicly filed complaint. Therefore, the complaint document itself does not provide sufficient detail to identify the specific accused products or describe their technical functionality and market context.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges direct infringement of the ’527 Patent and direct and indirect infringement of the ’790 and ’242 Patents (Compl. ¶¶ 13, 19, 23, 28, 32). For all three patents, the complaint's substantive infringement allegations are made by incorporating external claim chart exhibits by reference (Compl. ¶¶ 16, 25, 34). As these exhibits were not provided with the complaint, a detailed element-by-element analysis is not possible. The narrative infringement theory is that the "Exemplary Defendant Products practice the technology claimed" by the patents-in-suit and "satisfy all elements of the Exemplary [...] Patent Claims" (Compl. ¶¶ 15, 24, 33).

• Identified Points of Contention:
  • ’527 Patent: A potential point of contention is whether the accused products contain a distinct "interface module" with a "memory means" that functions precisely as claimed—storing a predetermined number of image lines to match a downstream compression unit. The dispute may center on whether a modern, integrated system-on-a-chip architecture, which may use partitions of general-purpose memory, meets the structural and functional limitations of the claims.
  • ’790 and ’242 Patents: The infringement analysis for these patents may turn on the specific operation of the accused products' data-handling architecture. A key question is whether the products employ a "signal generator" that actively generates a signal "in response to the quantity of data in the memory" (e.g., a buffer-fill-level trigger), as required by the claims, or if they use a more generic bus management or DMA protocol that may not map directly onto the claimed functionality.

V. Key Claim Terms for Construction

’527 Patent

• The Term: "memory means coupled to said read control means for storing said predetermined number of image lines, said memory means capable of storing the same number of image lines as said built-in memory device" (Claim 1).
• Context and Importance: This limitation defines the central architectural feature of the invention: a purpose-sized buffer that eliminates the need for a separate, larger RAM. The outcome of the infringement analysis will likely depend on whether the accused devices possess a memory structure that meets this specific sizing and functional constraint.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent claims a "module," which could suggest a functional grouping of components rather than a strict physical structure, and the use of "means" language may invite a functional interpretation under 35 U.S.C. § 112(f) (’527 Patent, col. 4:3-8).
  • Evidence for a Narrower Interpretation: The specification repeatedly frames the invention as a solution to the problem of requiring an "extra memory 14" (’527 Patent, col. 1:49-55). The preferred embodiment describes a specific implementation where the memory "24" stores exactly 8 lines of image data to service an 8x8 pixel compression unit, suggesting a tight, one-to-one correspondence in capacity (’527 Patent, col. 3:6-9).

’790 Patent

• The Term: "a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory" (Claim 1).
• Context and Importance: This term describes the core "trigger" mechanism of the interface. Practitioners may focus on this term because its construction will determine whether a generic data-ready or bus-request signal in a modern SoC is sufficient to meet the claim, or if a more specific quantity-monitoring circuit is required.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The summary of the invention states the signal generator may produce either an "interrupt signal" or a "bus request signal," encompassing different types of system-level alerts (’790 Patent, col. 2:14-18).
  • Evidence for a Narrower Interpretation: The detailed description and Figure 2 show a specific embodiment where an "Interrupt Generator 48" compares the output of a "FIFO counter" ("Sc") to a "FIFO limit" ("SL") to generate the signal (’790 Patent, Fig. 2; col. 6:11-15). This could support an interpretation that the signal must be generated based on a specific, measured quantity of data, not just the mere presence of any data.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 Patents. The allegations are based on Defendant distributing "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents (Compl. ¶¶ 22, 31). The complaint states that knowledge for inducement arises at least from the date of service of the complaint (Compl. ¶¶ 23, 32).
• Willful Infringement: While the complaint does not use the word "willful," it alleges "Actual Knowledge of Infringement" for the ’790 and ’242 Patents, based on the service of the complaint and its attached claim charts (Compl. ¶¶ 21, 30). It further alleges that Defendant has continued its infringing conduct despite this knowledge, which could form the basis for a claim of post-suit willful infringement and a request for enhanced damages (Compl. ¶¶ 22, 31; Prayer for Relief ¶H).

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: The complaint's infringement contentions rely entirely on external exhibits not filed with the court. A threshold issue will be whether Plaintiff can produce discovery evidence sufficient to show that the internal hardware and software architecture of Defendant’s mass-market drone products maps onto the specific claim limitations of patents from the early 2000s.

2. Architectural Congruence: For the ’527 Patent, a central question will be one of definitional scope: can the term "memory means"..."capable of storing the same number of image lines" as a JPEG device be construed to read on a logical partition within a modern, unified memory architecture, or does it require a discrete, physically co-sized buffer as depicted in the patent’s embodiment?

3. Functional Specificity: For the ’790 and ’242 Patents, the case may turn on a question of functional operation: do the accused products’ data management systems merely provide a generic "data available" or bus-access signal, or do they contain a specific "signal generator" that triggers a processor alert based on the quantitative fill-level of a buffer, as the claim language and patent figures suggest?