Cedar Lane Tech Inc v. Motorola Solutions Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Motorola Solutions, Inc. (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01111, W.D. Tex., 10/26/2022
• Venue Allegations: Venue is alleged to be proper based on Defendant maintaining an established place of business in the Western District of Texas and committing alleged acts of infringement within the district.
• Core Dispute: Plaintiff alleges that certain of Defendant’s products infringe three patents related to digital image processing and interfacing between image sensors and other components like compression engines or host processors.
• Technical Context: The patents address methods for efficiently buffering and transferring digital image data, a core technological challenge in devices like digital cameras, scanners, and other imaging systems.
• Key Procedural History: The complaint does not mention any prior litigation or inter partes review proceedings. U.S. Patent No. 8,537,242 is a divisional of the application that resulted in U.S. Patent No. 6,972,790 and is subject to a terminal disclaimer, which may limit its enforceable term to that of the '790 patent.

Case Timeline

Date	Event
1999-06-01	'527 Patent Priority Date
2000-01-21	'790 & '242 Patents Priority Date
2000-12-21	'790 Patent Application Filing Date
2002-10-29	'527 Patent Issue Date
2005-10-27	'242 Patent Application Filing Date
2005-12-06	'790 Patent Issue Date
2013-09-17	'242 Patent Issue Date
2022-10-26	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527: “Module and method for interfacing analog/digital converting means and JPEG compression means” (Issued Oct. 29, 2002)

The Invention Explained

• Problem Addressed: The patent's background describes that conventional digital imaging systems often required a separate, "extra memory" buffer (like a RAM chip) to sit between the analog-to-digital (A/D) converter and the dedicated JPEG compression hardware. This buffer was needed to re-format a simple line-by-line data stream into the block-based structure (e.g., 8x8 pixels) that JPEG algorithms require, adding cost and hardware complexity to the system. (’527 Patent, col. 2:37-57).
• The Patented Solution: The invention proposes an interface module that eliminates the need for this extra external memory. The module contains its own internal memory and control logic. It reads a predetermined number of image lines (e.g., eight lines) from the A/D converter into its memory, and then its output controller feeds the data to the JPEG compression device in correctly-sized image blocks, ready for compression. (’527 Patent, Abstract; col. 3:1-18; Fig. 2).
• Technical Importance: This design sought to reduce the bill of materials and overall system cost for imaging devices by integrating this buffering and re-formatting function into a single interface module. (’527 Patent, col. 2:54-60).

Key Claims at a Glance

• The complaint asserts infringement of "one or more claims," with the specific "Exemplary '527 Patent Claims" identified in an external exhibit not attached to the complaint (Compl. ¶13, ¶15). Independent claim 1 is representative and includes the following essential elements:
  • A module comprising:
  • "read control means" for sequentially reading a predetermined number of image lines from an A/D converter and generating a control signal;
  • "memory means" for storing those image lines, with a capacity to store the same number of lines as a memory built into the JPEG compression device; and
  • "output control means", responsive to the control signal, for reading an image block from the memory means and forwarding it to the JPEG device's built-in memory.
• The complaint reserves the right to assert other claims, which may include dependent claims. (Compl. ¶13).

U.S. Patent No. 6,972,790: “Host interface for imaging arrays” (Issued Dec. 6, 2005)

The Invention Explained

• Problem Addressed: The patent notes that CMOS image sensors typically output a continuous "video style" stream of pixel data synchronized to a master clock. This output format is fundamentally incompatible with the memory-mapped, random-access interfaces of general-purpose microprocessors, necessitating "additional glue logic" that diminishes the cost-effectiveness of using integrated CMOS sensor technology. (’790 Patent, col. 1:37-58).
• The Patented Solution: The patent describes an on-chip interface that bridges this gap. The interface uses a memory, such as a first-in-first-out (FIFO) buffer, to receive and store image data at the sensor's native speed. When the amount of data in the buffer reaches a certain level, a signal generator alerts the host processor (e.g., via an interrupt). A control circuit then manages the transfer of the buffered data over the system bus to the processor at a rate the processor dictates. (’790 Patent, Abstract; col. 2:4-14; Fig. 2).
• Technical Importance: By integrating this buffering and handshaking logic onto the same die as the sensor, the invention allows a host processor to communicate with the image sensor as if it were a standard memory peripheral, simplifying system design and reducing external component count. (’790 Patent, col. 1:59-66).

Key Claims at a Glance

• The complaint asserts infringement of "one or more claims," with specific claims identified in an external exhibit not attached to the complaint (Compl. ¶19, ¶24). Independent claim 1 is representative and includes the following essential elements:
  • An interface comprising:
  • "a memory" for storing imaging array data and clocking signals at a rate determined by the clocking signals;
  • "a signal generator" for generating a signal to the processor system "in response to the quantity of data in the memory"; and
  • "a circuit" for controlling the data transfer from the memory at a rate determined by the processor system.
• The complaint reserves the right to assert other claims. (Compl. ¶19).

Multi-Patent Capsule: U.S. Patent No. 8,537,242

• Patent Identification: U.S. Patent No. 8,537,242, “Host interface for imaging arrays,” issued Sep. 17, 2013. (Compl. ¶11).
• Technology Synopsis: As a divisional of the application for the '790 patent, this patent covers similar subject matter. It describes an interface for processing imaging signals, specifically one that stores incoming image data in a FIFO memory, uses a counter to track the amount of data in the memory, and generates a request (e.g., a bus request) to a processor system to initiate data transfer when the data count reaches a predetermined limit. (’242 Patent, Abstract; col. 2:1-20).
• Asserted Claims: The complaint alleges infringement of "one or more claims" of the '242 patent, with specific claims identified in the (missing) Exhibit 6. (Compl. ¶28, ¶33).
• Accused Features: The complaint alleges that the "Exemplary Defendant Products" practice the technology claimed by the '242 Patent, but provides no specific details, instead incorporating them by reference from Exhibit 6. (Compl. ¶33).

III. The Accused Instrumentality

• Product Identification: The complaint does not identify any of Defendant’s products or services by name. It refers to the accused instrumentalities as the "Exemplary Defendant Products," which are purportedly identified in claim chart exhibits that were not filed with the complaint. (Compl. ¶13, ¶19, ¶28).
• Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It states that Defendant makes, uses, sells, and imports these products, and that they are tested internally by employees, but all specific technical details are incorporated by reference from the missing exhibits. (Compl. ¶13-15).

IV. Analysis of Infringement Allegations

The complaint alleges infringement but incorporates the specific claim element-by-element comparisons in Exhibits 4, 5, and 6, which are not publicly available. Therefore, a detailed claim chart summary cannot be constructed. The narrative infringement theories are summarized below.

No probative visual evidence provided in complaint.

• '527 Patent Infringement Allegations: The complaint asserts direct infringement, alleging that the "Exemplary Defendant Products" practice the technology of the '527 patent and that their features "satisfy all elements of the Exemplary '527 Patent Claims." (Compl. ¶13, ¶15). The specific mapping of product features to claim elements is contained within the referenced Exhibit 4. (Compl. ¶16).
• '790 Patent Infringement Allegations: The complaint asserts direct infringement, alleging that the accused products practice the claimed technology and satisfy all elements of the asserted claims from the '790 patent. (Compl. ¶19, ¶24). The detailed infringement theory is contained within the referenced Exhibit 5. (Compl. ¶25).
• Identified Points of Contention:
  • Scope Questions: For the '527 patent, a key dispute may arise over the interpretation of the "read control means" and "output control means" limitations. As means-plus-function elements, their scope is tied to the specific structures disclosed in the patent. A question for the court will be whether the accused products, which may use highly integrated systems-on-a-chip (SoCs), contain structures that are the same as or equivalent to the distinct control devices depicted in the patent's specification.
  • Technical Questions: For the '790 patent, a central technical question may be whether the accused interface generates a signal to the host processor "in response to the quantity of data in the memory," as required by claim 1. The analysis will depend on evidence showing that the data transfer is triggered by the buffer's fill level, as opposed to other potential control schemes such as a fixed-timing DMA or a processor-polled mechanism.

V. Key Claim Terms for Construction

'527 Patent

• The Term: "read control means" / "output control means" (from Claim 1).
• Context and Importance: These terms are drafted in means-plus-function format under 35 U.S.C. § 112(f), meaning their scope is not limitless but is confined to the specific structures described in the patent's specification that perform the recited functions, plus their equivalents. Practitioners may focus on these terms because the entire infringement case will depend on first identifying the corresponding structure in the patent (the "read control device 22" and "output control device 23") and then determining whether the accused products contain structures that are equivalent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue for a broader scope of equivalents by focusing on the high-level functional description in the claims.
  • Evidence for a Narrower Interpretation: The specification explicitly discloses the structure as "read control device 22" and "output control device 23," which are shown as distinct blocks in Figure 2. (’527 Patent, Fig. 2). The detailed description explains that device 22 reads image lines until a count is met, then generates a signal (221) to activate device 23, which in turn reads out formatted image blocks. (’527 Patent, col. 3:1-18). This specific, disclosed implementation will likely narrow the scope of the claims to this structure and its close equivalents.

'790 Patent

• The Term: "a memory for storing imaging array data and clocking signals" (from Claim 1).
• Context and Importance: The requirement to store "clocking signals" in addition to "imaging array data" is a point of potential ambiguity. Practitioners may focus on this term because while a buffer's operation is timed by clock signals, it is not always the case that the clock signals themselves are "stored" as data to be read out later. The dispute will likely center on whether using clocks as timing inputs for a memory write operation satisfies this limitation.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification states that the "FIFO buffer 44 receives array data Da... clocking signals C... clocking signals CR and CF" which are "bundled onto a single bus 51 for storage in the buffer 44." (’790 Patent, col. 5:6-14). This language may support an interpretation that the clock signals themselves are treated as data to be stored.
  • Evidence for a Narrower Interpretation: A party could argue that the clock signals (Cp, CR, CF) are described as inputs that control the buffer's operation (e.g., timing the shifting of data into registers) rather than data that is stored in the memory cells for later retrieval. The ultimate purpose of the memory is to buffer the "imaging array data," suggesting the storage of clock signals may be merely incidental to this primary function.

VI. Other Allegations

• Indirect Infringement: For the '790 and '242 patents, Plaintiff alleges induced infringement. The complaint alleges this is based on Defendant distributing "product literature and website materials" that instruct customers to use the accused products in an infringing manner. (Compl. ¶22-23, ¶31-32).
• Willful Infringement: For the '790 and '242 patents, the complaint alleges that service of the complaint itself provides Defendant with "actual knowledge" of infringement. It is alleged that any continued infringement after this date is willful. (Compl. ¶21-22, ¶30-31). The complaint does not allege any pre-suit knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

1. Evidentiary Sufficiency: A threshold issue is whether the factual allegations, which are contained entirely within non-public exhibits, meet the plausibility standard for pleading patent infringement. The viability of the case will depend on whether those exhibits provide a sufficiently detailed and non-conclusory explanation of how specific features of the accused Motorola products map to the elements of the asserted patent claims.
2. Structural Correspondence: For the '527 patent, the case may turn on a question of structural equivalence. Can the functional blocks claimed as "read control means" and "output control means" find corresponding, equivalent structures within the highly integrated architecture of the accused products, or is there a fundamental mismatch between the patent's disclosed implementation and the technology used by the Defendant?
3. Functional Operation: For the '790 and '242 patents, a key question will be one of functional operation. Does the accused sensor interface alert the host processor "in response to the quantity of data in the memory" as the claims require? The outcome may depend on evidence demonstrating the specific trigger mechanism for data transfers in the accused systems and whether it aligns with the quantity-responsive method described in the patents.