Cedar Lane Tech Inc v. STMicroelectronics Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: STMicroelectronics, Inc. (Delaware)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01120, W.D. Tex., 10/26/2022
• Venue Allegations: Venue is alleged to be proper in the Western District of Texas because the defendant, STMicroelectronics, Inc., maintains an established place of business in the district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products infringe two patents related to an interface architecture for transferring data from a CMOS image sensor to a host processor system.
• Technical Context: The technology addresses the mismatch between the constant data output rate of an image sensor and the variable processing availability of a general-purpose CPU in devices like digital cameras and embedded systems.
• Key Procedural History: The complaint notes that the '242 Patent is a divisional of the application that resulted in the '790 Patent, indicating a shared specification and priority date. No other procedural history is mentioned.

Case Timeline

Date	Event
2000-01-21	Priority Date for '790 and '242 Patents
2005-12-06	U.S. Patent No. 6,972,790 Issues
2013-09-17	U.S. Patent No. 8,537,242 Issues
2022-10-26	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,972,790 - Host interface for imaging arrays, issued Dec. 6, 2005

The Invention Explained

• Problem Addressed: The patent’s background explains that the continuous, video-style data stream from an image sensor is fundamentally "incompatible with the data interface of commercial microprocessors" without requiring "additional glue logic" (Compl. Ex. 1, '790 Patent, col. 1:46-53). This extra hardware diminishes the cost and integration advantages of using CMOS technology for image sensors ('790 Patent, col. 1:62-67).
• The Patented Solution: The invention proposes an interface, preferably integrated onto the same semiconductor die as the sensor, that mediates between the sensor and a host processor ('790 Patent, col. 2:25-34). The interface uses a memory buffer (e.g., a FIFO) to store image data as it arrives from the sensor. When the buffer accumulates a certain amount of data, a signal generator alerts the processor, which can then read the data from the buffer at its own pace ('790 Patent, Abstract). This decouples the sensor's fixed data-capture rate from the processor's variable data-access rate.
• Technical Importance: This architecture allows a processor to perform other tasks and retrieve image data only when a sufficient amount is ready, preventing data loss without monopolizing the CPU ('790 Patent, col. 5:15-19).

Key Claims at a Glance

The complaint does not identify specific claims in its body, instead referring to an external exhibit not provided with the complaint (Compl. ¶12). Independent claim 1 is representative of the apparatus claims.

• Independent Claim 1:
  • An interface for receiving data from an image sensor and for transfer to a processor system.
  • A memory for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • A signal generator that generates a signal for the processor system in response to the quantity of data in the memory.
  • A circuit that controls the transfer of data from the memory at a rate determined by the processor system.
• The complaint reserves the right to assert other claims, including dependent claims (Compl. ¶12).

U.S. Patent No. 8,537,242 - Host interface for imaging arrays, issued Sep. 17, 2013

The Invention Explained

• Problem Addressed: As a divisional of the '790 Patent's application, this patent addresses the same technical problem: the incompatibility between an image sensor's raw output and a microprocessor's data interface (Compl. Ex. 2, '242 Patent, col. 1:45-52).
• The Patented Solution: The '242 Patent claims the method of operating the interface system. The claimed method involves the steps of receiving image data into a FIFO memory, using a counter to track the amount of data in that memory, comparing the count against a predefined limit, and then generating an interrupt signal to the processor, which triggers the data transfer from the memory ('242 Patent, Claim 1).
• Technical Importance: The method claims provide a different form of protection for the same core inventive concept of decoupling the image sensor from the host processor via a buffered, interrupt-driven communication scheme ('242 Patent, col. 6:1-5).

Key Claims at a Glance

The complaint does not identify specific claims, referring to an external exhibit not provided with the complaint (Compl. ¶21). Independent claim 1 is representative of the method claims.

• Independent Claim 1:
  • A method of processing imaging signals, comprising:
  • receiving image data from an imaging array;
  • storing the image data in a FIFO memory;
  • updating a FIFO counter to maintain a count of the image data;
  • comparing the count of the FIFO counter with a FIFO limit;
  • generating an interrupt signal to a processor when the count meets a predetermined relationship to the limit; and
  • transferring image data from the FIFO memory to the processor in response to the interrupt signal.
• The complaint reserves the right to assert other claims (Compl. ¶21).

III. The Accused Instrumentality

Product Identification

The complaint does not name any specific accused products in the body of the pleading. It refers to "Exemplary Defendant Products" that are purportedly identified in external claim chart exhibits, which were not filed with the complaint (Compl. ¶12, ¶17, ¶21, ¶26).

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context.
No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint alleges that the "Exemplary Defendant Products" practice the technology claimed in the patents-in-suit and satisfy all elements of the asserted claims (Compl. ¶17, ¶26). However, it does not provide a narrative infringement theory or any specific factual allegations mapping product features to claim limitations. Instead, it incorporates by reference external claim chart exhibits (Exhibits 3 and 4) that were not included with the filed complaint (Compl. ¶18, ¶27). As a result, a detailed analysis of the infringement allegations is not possible based on the provided documents.

V. Key Claim Terms for Construction

'790 Patent

The Term: "at a rate determined by the processor system" (from Claim 1)

• Context and Importance: This term is central to the invention's claimed decoupling of the sensor and processor. Its construction will define how direct the processor's control over the data transfer must be. Practitioners may focus on this term because the nature of this "determination" (e.g., direct command vs. indirect latency) could be a primary point of non-infringement.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the processor responding to an interrupt to "unload" the buffer, which allows it to "multi-task" ('790 Patent, col. 5:15-19). A party could argue this supports a construction where the processor's general availability and response latency indirectly "determines" the transfer rate, even without an explicit rate-setting command.
  • Evidence for a Narrower Interpretation: The claim language requires the circuit to control the transfer "at a rate determined by" the processor. A party could argue this implies a more active role where the processor system provides a specific rate parameter or command, rather than merely being the recipient of an interrupt.

The Term: "a memory" (from Claim 1)

• Context and Importance: The breadth of this term affects the types of hardware architectures that fall within the claim's scope. Whether it is limited to a specific type of buffer, like a FIFO, will be a key question.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent abstract explicitly states, "The memory may be a first-in first-out (FIFO) buffer or an addressable memory" ('790 Patent, Abstract). This language provides strong support for a construction that is not limited to one specific type of memory.
  • Evidence for a Narrower Interpretation: The patent’s detailed description and figures focus heavily on a FIFO buffer embodiment (e.g., FIG. 2, FIG. 5) ('790 Patent, col. 5:6-14). A party might argue these specific disclosures should inform and potentially limit the scope of the broader term used in the claim.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for both patents. The factual basis alleged is that Defendant distributes "product literature and website materials" that instruct end users on how to use the accused products in an infringing manner (Compl. ¶15, ¶24). Knowledge and intent are alleged to exist at least from the date the complaint was served (Compl. ¶16, ¶25).
• Willful Infringement: The complaint does not use the term "willful." However, it alleges that service of the complaint constitutes "Actual Knowledge of Infringement" and that Defendant "continues to make, use, test, sell, offer for sale, market, and/or import" infringing products despite this knowledge (Compl. ¶14-15, ¶23-24). These allegations form a basis for a claim of post-suit willful infringement and potential enhanced damages.

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of procedural sufficiency: Does the complaint, which identifies accused products and infringement theories only by reference to external, unprovided exhibits, state a plausible claim for relief under the Twombly/Iqbal pleading standard, or is it vulnerable to a motion to dismiss?
• A key claim construction question will be one of definitional scope: How broadly will the court construe the phrase "at a rate determined by the processor system"? Resolution will likely turn on whether indirect control, such as a processor's delayed response to an interrupt, satisfies the limitation, or if a more direct command or rate-setting mechanism is required.
• Assuming the case proceeds, a core evidentiary question will be one of operational correspondence: Once the accused products are fully analyzed, does their architecture for managing data flow from sensor to processor function in the manner specifically recited by the claims, particularly regarding the generation of a signal "in response to the quantity of data in the memory"?