DCT

6:22-cv-01140

Cedar Lane Tech Inc v. Amlogic Shanghai Co Ltd

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 6:22-cv-01140, W.D. Tex., 10/31/2022
  • Venue Allegations: Venue is alleged to be proper because the Defendant is a foreign corporation.
  • Core Dispute: Plaintiff alleges that Defendant’s semiconductor products infringe patents related to a host interface for managing the transfer of data from an imaging array to a processor system.
  • Technical Context: The technology addresses the challenge of efficiently moving image data from a sensor to a processing unit, a fundamental operation in devices like digital cameras, smartphones, and other systems with integrated imaging capabilities.
  • Key Procedural History: The complaint does not mention any prior litigation, licensing history, or administrative proceedings related to the patents-in-suit.

Case Timeline

Date Event
2000-01-21 Priority Date for ’790 and ’242 Patents
2005-12-06 U.S. Patent No. 6,972,790 Issued
2013-09-17 U.S. Patent No. 8,537,242 Issued
2022-10-31 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,972,790, Host interface for imaging arrays (issued Dec. 6, 2005)

The Invention Explained

  • Problem Addressed: The patent describes a problem where the data output from CMOS image sensors, which operate at a fixed clock rate, is "incompatible with the data interface of commercial microprocessors" without using "additional glue logic" (U.S. Patent No. 6,972,790, col. 1:46-52). This additional hardware diminishes the cost and integration advantages of using CMOS technology for imaging.
  • The Patented Solution: The invention proposes an integrated interface that decouples the image sensor's fixed data rate from the processor's variable access rate. It uses a memory, such as a First-In First-Out (FIFO) buffer, to temporarily store image data as it arrives from the sensor. The interface then generates a signal, such as a processor interrupt, when a sufficient quantity of data has accumulated, allowing the processor to read the data from the memory at its own pace (U.S. Patent No. 6,972,790, Abstract; col. 2:4-14). This architecture is intended to be integrated onto the same semiconductor die as the image sensor, preserving the benefits of a single-chip solution (U.S. Patent No. 6,972,790, col. 2:25-32).
  • Technical Importance: This approach provides a standardized way to bridge the timing gap between specialized, high-rate sensor hardware and general-purpose processors, a common challenge in system-on-a-chip (SoC) design.

Key Claims at a Glance

  • The complaint does not specify which claims are asserted, referring only to the "Exemplary '790 Patent Claims" (Compl. ¶12).
  • Independent claim 1, an apparatus claim, recites the essential elements of the interface:
    • A memory for storing imaging array data and clocking signals at a rate determined by the clocking signals.
    • A signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory.
    • A circuit for controlling the transfer of the data from the memory at a rate determined by the processor system.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,537,242, Host interface for imaging arrays (issued Sep. 17, 2013)

The Invention Explained

  • Problem Addressed: As a divisional of the application that led to the ’790 Patent, the ’242 Patent addresses the same technical problem of incompatibility between image sensor data streams and microprocessor interfaces (U.S. Patent No. 8,537,242, col. 1:43-54).
  • The Patented Solution: The ’242 Patent claims a method for processing imaging signals, rather than an apparatus. The claimed method involves receiving image data, storing it in a FIFO memory, maintaining a count of the data in that memory, comparing the count to a predefined limit, and then generating an interrupt to signal a processor to transfer the data (U.S. Patent No. 8,537,242, Claim 1). This shifts the focus from the physical components of the interface to the specific sequence of operations performed to manage the data flow.
  • Technical Importance: Claiming the process as a method provides a different dimension of protection for the same core invention, covering the operational steps of the interface rather than just its structural components.

Key Claims at a Glance

  • The complaint refers to "Exemplary '242 Patent Claims" without specifying claim numbers (Compl. ¶21).
  • Independent claim 1, a method claim, recites the essential steps:
    • Receiving image data from an imaging array.
    • Storing the image data in a FIFO memory.
    • Updating a FIFO counter to maintain a count of the image data in the memory.
    • Comparing the count of the FIFO counter with a FIFO limit.
    • Generating an interrupt signal to request a processor to transfer image data based on the comparison and an enable signal.
    • Transferring the image data from the FIFO memory to the processor in response to the interrupt.
  • The complaint does not explicitly reserve the right to assert dependent claims.

III. The Accused Instrumentality

Product Identification

The complaint does not identify specific accused products by name. It refers generally to "Exemplary Defendant Products" that are identified in claim charts attached as exhibits, which were not filed with the complaint (Compl. ¶12, ¶21).

Functionality and Market Context

The complaint alleges that the accused products are semiconductor devices that "practice the technology claimed" by the patents-in-suit (Compl. ¶17, ¶26). No specific technical details about the operation or market position of the accused products are provided in the body of the complaint.

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not contain claim charts or a detailed, element-by-element breakdown of its infringement theories. It incorporates by reference external Exhibits 3 and 4, which were not provided with the filed complaint, for this purpose (Compl. ¶18, ¶27). The narrative allegations state that the "Exemplary Defendant Products" satisfy all elements of the asserted claims, either literally or under the doctrine of equivalents (Compl. ¶12, ¶21). The complaint does not provide sufficient detail for analysis of how any specific accused product meets any specific claim limitation.

Identified Points of Contention

  • Evidentiary Question: A central issue will be whether Plaintiff can produce sufficient technical evidence to demonstrate that Defendant's products, which are likely complex SoCs, contain an interface that operates in the specific manner recited in the claims.
  • Technical Question (’790 Patent): For the apparatus claims, a question may arise as to whether the architecture of the accused products includes a "memory," a "signal generator," and a "circuit for controlling" that map directly onto the claimed elements and their functional relationship, particularly the requirement that the signal generator acts "in response to the quantity of data in the memory" (U.S. Patent No. 6,972,790, col. 8:10-12).
  • Technical Question (’242 Patent): For the method claims, the analysis will focus on whether the accused products necessarily perform the exact sequence of steps claimed, including the specific logic of "updating a FIFO counter," "comparing the count...with a FIFO limit," and "generating an interrupt signal" based on that comparison (U.S. Patent No. 8,537,242, col. 8:57-65).

V. Key Claim Terms for Construction

  • The Term: "a memory for storing imaging array data and clocking signals" (’790 Patent, Claim 1).

    • Context and Importance: This term appears in the main apparatus claim. Practitioners may focus on this term because its interpretation determines what must be stored in the memory. The dispute could center on whether the claim requires the literal storage of the "clocking signals" themselves, or merely storing the image data in accordance with the timing of those signals.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent’s objective is to solve a timing mismatch problem. Language describing the memory storing data "at a rate determined by the clocking signals" (U.S. Patent No. 6,972,790, col. 2:7-8) may support an interpretation that the signals' function is to time the storage of image data, not to be stored themselves.
      • Evidence for a Narrower Interpretation: The plain language of the claim recites storing "imaging array data and clocking signals." A party could argue that this conjunctive "and" requires that both data types be stored in the memory.

  • The Term: "in response to the quantity of data in the memory" (’790 Patent, Claim 1).

    • Context and Importance: This phrase links the state of the memory buffer to the generation of the signal to the processor. The key question is the nature of the required "response."
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The abstract states the signal is generated "In response to the quantity of data in the memory," suggesting a general causal link without specifying the mechanism. This could cover any implementation where the fill level of the buffer triggers the signal.
      • Evidence for a Narrower Interpretation: The detailed description discloses a specific embodiment where an "interrupt generator 48 compares the FIFO counter output Sc and the FIFO limit S L" to generate the interrupt (U.S. Patent No. 6,972,790, col. 6:11-14). This could support an argument that the "response" requires a specific comparison against a predetermined threshold, not just any dependency on the data quantity.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges induced infringement for both patents. It claims Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents (Compl. ¶15, ¶24). Specific evidence for this allegation is cited as being in the unfiled Exhibits 3 and 4 (Compl. ¶15, ¶24).
  • Willful Infringement: The complaint does not use the term "willful." It pleads "Actual Knowledge of Infringement" based on the service of the complaint itself (Compl. ¶14, ¶23). This allegation appears to lay the groundwork for a claim of post-filing enhanced damages rather than pre-suit willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Evidentiary Sufficiency: The complaint is factually sparse, relying on non-public exhibits for all substantive infringement details. A primary question will be whether Plaintiff can produce sufficient technical evidence from those exhibits and through discovery to show that Defendant’s products practice the specific structural and methodical limitations of the patents.
  2. Claim Scope and Modern Equivalence: A core issue will be one of definitional scope. Can the claim terms, drafted based on early 2000s technology, be construed to read on the potentially more complex and integrated data management architectures found in modern semiconductor systems? The dispute may turn on whether the accused products' functionality is merely an updated version of the claimed invention or a fundamentally different technical approach.
  3. Apparatus vs. Method: The assertion of both an apparatus patent (’790) and a corresponding method patent (’242) raises the question of whether Plaintiff can meet the distinct proof requirements for each. The court will need to determine not only if the accused products contain infringing structures, but also if they necessarily perform the infringing sequence of steps in their normal operation.