Cedar Lane Tech Inc v. THine Electronics Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: THine Electronics, Inc. (Japan)
  • Plaintiff’s Counsel: Rabicoff Law LLC
• Case Identification: 6:22-cv-01145, W.D. Tex., 10/31/2022
• Venue Allegations: Venue is alleged to be proper on the basis that the Defendant is a foreign corporation.
• Core Dispute: Plaintiff alleges that Defendant’s electronics products infringe three U.S. patents related to methods and modules for interfacing image sensors with data processing and compression hardware.
• Technical Context: The technology concerns the efficient transfer of image data from a sensor (like those in digital cameras or scanners) to a processor or compression chip, a foundational process in digital imaging devices.
• Key Procedural History: The complaint does not allege any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
1999-06-01	’527 Patent Priority Date
2000-01-21	’790 and ’242 Patents Priority Date
2002-10-29	’527 Patent Issue Date
2005-12-06	’790 Patent Issue Date
2013-09-17	’242 Patent Issue Date
2022-10-31	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued October 29, 2002

The Invention Explained

• Problem Addressed: The patent describes a problem in digital imaging systems where an extra, costly memory component (typically RAM) was required to sit between an analog-to-digital (A/D) converter and a JPEG compression chip. This extra memory was needed to buffer image data, which arrives line-by-line from the A/D converter, and re-format it into the block-based structure (e.g., 8x8 pixels) required by the JPEG compression algorithm (’527 Patent, col. 1:40-54).
• The Patented Solution: The invention proposes an interface module that eliminates the need for this extra external memory. The module contains its own internal memory, which is sized to store a specific number of image lines (e.g., eight lines). Once this internal memory is full, the module’s control logic reads out correctly-sized image blocks (e.g., 8x8 pixels) and sends them directly to the JPEG compression device, thereby managing the data flow and formatting internally (’527 Patent, Abstract; col. 2:3-20).
• Technical Importance: This design aimed to reduce the cost and complexity of digital imaging hardware, such as scanners and digital cameras, by omitting a separate memory component from the system architecture (’527 Patent, col. 1:55-57; col. 2:21-23).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, instead referring to "Exemplary '’527 Patent Claims" in an external exhibit not attached to the complaint (Compl. ¶13). The first independent apparatus claim is Claim 1, and the first independent method claim is Claim 8.
• Independent Claim 1 recites the key elements of the module:
  • "read control means" for reading a "predetermined number of image lines" from the A/D converter.
  • "memory means" for storing those image lines, with a capacity capable of storing the same number of lines as the JPEG device's built-in memory.
  • "output control means" for reading an "image block" from the memory means and sending it to the JPEG device's built-in memory.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued December 6, 2005

The Invention Explained

• Problem Addressed: The patent notes an incompatibility between the "video style output" of CMOS image sensors, which stream pixel data at a fixed clock rate, and the data interfaces of commercial microprocessors, which are designed for random access using address and control signals. Bridging this gap conventionally required "additional glue logic" and memory, diminishing the cost and integration advantages of using CMOS technology for "system-on-a-chip" designs (’790 Patent, col. 1:38-61).
• The Patented Solution: The invention describes an interface, intended to be integrated on the same semiconductor die as the image sensor, that manages the data transfer. This interface uses an internal memory (such as a FIFO buffer) to receive and store image data at the sensor's native rate. When the amount of data in the memory reaches a certain level, the interface generates a signal (e.g., a processor interrupt) to alert a host processor. The processor can then read the buffered data from the interface at its own speed and under its own control, decoupling the two systems' timing (’790 Patent, Abstract; col. 2:4-13).
• Technical Importance: This architecture allows a processor to interface directly with a CMOS image sensor without needing complex external logic, facilitating smaller, cheaper, and more integrated imaging systems (’790 Patent, col. 1:62-66).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, instead referring to "Exemplary '’790 Patent Claims" in an external exhibit not attached to the complaint (Compl. ¶19). The first independent claim is Claim 1.
• Independent Claim 1 recites the key elements of the interface:
  • "a memory" for storing imaging array data at a rate determined by the sensor's clocking signals.
  • "a signal generator" that generates a signal for the processor "in response to the quantity of data in the memory."
  • "a circuit" for controlling the transfer of data from the memory at a rate determined by the processor system.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," Issued September 17, 2013

• Patent Identification: U.S. Patent No. 8,537,242, "Host interface for imaging arrays," Issued September 17, 2013 (Compl. ¶11).
• Technology Synopsis: As a divisional of the application leading to the ’790 Patent, this patent addresses the same problem of efficiently interfacing a CMOS image sensor with a processor. The invention is a method of processing imaging signals that involves storing incoming data in a FIFO memory, maintaining a count of the data in that memory, and generating a request (such as an interrupt or a bus request) for data transfer when the count reaches a predetermined limit (’242 Patent, Abstract; col. 2:1-20).
• Asserted Claims: The complaint refers to "Exemplary '’242 Patent Claims" in an external exhibit not attached to the complaint and thus does not identify specific claims (Compl. ¶28).
• Accused Features: The complaint alleges infringement by "Exemplary Defendant Products" but does not specify which features of those products are accused of infringing this particular patent (Compl. ¶28, ¶33).

III. The Accused Instrumentality

• Product Identification: The complaint refers to "Exemplary Defendant Products" that are identified in Exhibits 4, 5, and 6 (Compl. ¶13, ¶19, ¶28). These exhibits were not filed with the complaint, so the specific accused products cannot be identified.
• Functionality and Market Context: The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It makes only general allegations that the products are made, used, and sold by Defendant and that they practice the claimed technology (Compl. ¶13, ¶19, ¶28).
• No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint does not include the referenced claim chart exhibits (Exhibits 4, 5, and 6) that detail the infringement allegations (Compl. ¶16, ¶25, ¶34). The infringement theory is stated in conclusory terms, alleging that the "Exemplary Defendant Products practice the technology claimed" and "satisfy all elements" of the asserted claims (Compl. ¶15, ¶24, ¶33). Without the claim charts or technical details of the accused products, a detailed analysis is not possible.

• Identified Points of Contention: Based on the patent language and the general nature of the allegations, several high-level questions may become central to the dispute.
  • Technical Questions: A primary factual question will be whether discovery reveals that the accused products operate in the manner required by the claims. For the ’790 Patent, for example, what evidence demonstrates that the accused interface generates a processor signal specifically "in response to the quantity of data in the memory," as opposed to being triggered by other system events?
  • Scope Questions: For the ’527 Patent, a key issue may be whether the accused products contain distinct components corresponding to the claimed "read control means", "memory means", and "output control means". The interpretation of this "means-plus-function" language and its application to the accused product architecture will be a focal point.

V. Key Claim Terms for Construction

For the ’527 Patent:

• The Term: "memory means" (from Claim 1)
• Context and Importance: The characteristics of this memory element are central to the invention's stated goal of eliminating a separate, external memory. Practitioners may focus on this term because its construction will determine whether any internal buffer infringes, or only a buffer with the specific characteristics and capacity described in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification, when discussing prior art, refers to a memory device as potentially being "a random access memory or any memory device," language that could be argued to support a broader definition not tied to a specific type or size (’527 Patent, col. 1:35-36).
  • Evidence for a Narrower Interpretation: The summary of the invention and preferred embodiments state that the "memory device can save the same number of image lines as the memory device built-in the JPEG compression device" (e.g., 8 lines), suggesting its size is functionally tied to the downstream compression block (’527 Patent, col. 2:8-12).

For the ’790 Patent:

• The Term: "in response to the quantity of data in the memory" (from Claim 1)
• Context and Importance: This phrase defines the specific trigger for the interface to signal the processor. The infringement analysis will hinge on whether the accused products' signaling logic is causally linked to the buffer's fill level. This term distinguishes the claimed invention from systems that might use simple periodic or clock-based signaling.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party might argue this language covers any system where the buffer fill level is a factor, even if not the sole or direct cause, in the decision to generate a signal.
  • Evidence for a Narrower Interpretation: The detailed description discloses a specific implementation where an "interrupt generator compares the FIFO counter output...and the FIFO limit," and asserts the signal if the count meets or exceeds the limit. This points to a direct, threshold-based triggering mechanism (’790 Patent, col. 6:11-15).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for the ’790 and ’242 patents. The allegations are based on Defendant selling the accused products and distributing "product literature and website materials" that allegedly instruct customers and end users on how to use the products in an infringing manner (Compl. ¶22, ¶23, ¶31, ¶32).
• Willful Infringement: The complaint alleges that Defendant has had "Actual Knowledge of Infringement" for the ’790 and ’242 patents since the service of the complaint itself (Compl. ¶21, ¶30). No facts are alleged to support pre-suit knowledge, suggesting the willfulness claim is based on alleged post-filing conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of evidentiary proof: As the complaint lacks specific technical details about the accused products, the case will depend on whether discovery can establish that Defendant’s products contain the precise memory architectures and control logic recited in the claims. For example, does an accused product’s interface buffer data and then signal a processor because a data quantity threshold has been met, as required by the ’790 patent family?

2. The dispute will likely involve a question of claim construction and scope: For the ’527 patent, can the term "memory means" be construed to cover any generic internal buffer, or is it limited to a memory specifically sized and controlled to match the block-based input requirements of a downstream JPEG compressor?

3. A third key question will relate to causality in infringement: For the ’790 and ’242 patents, the infringement case appears to rest on proving a specific functional relationship—that a signal is generated "in response to the quantity of data." The case may turn on whether there is a direct causal link or a more attenuated relationship between the buffer fill level and processor signaling in the accused products.